F81867 Datasheet, PDF (49/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
TSI Offset Register ⎯ Index 0Dh
Bit
Name
R/W Reset Default
Description
This byte is used as the offset to be added to the CPU temperature
7-0
TSI_OFFSET
R/W 5VSB 0 _{reading of AMD_TSI.}
The range of this register is -128 ~ 127^ºC.
Configuration Register ⎯ Index 0Fh
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
1-0 DIG_RATE_SEL R/W 5VSB
0 Reserved.
0 ^{Reserved for Fintek use only}
TSI Temperature 0 – Index E0h
Bit
Name
R/W Reset Default
Description
This is the AMD TSI reading if AMD TSI enable.
TSI_TEMP0
R/W 5VSB
And will be highest temperature among CPU, MCH and PCH if Intel
-
temperature interface enable. The range is 0~255^ºC. To access this byte,
MCH_BANK_SEL must set to “0”.
This byte is used as multi-purpose:
1. The received data of receive protocol.
7-0
2. The first received byte of read word protocol.
I2C_DATA0
R/W 5VSB 8’h00
3. The 10^th received byte of read block protocol.
4. The sent data for send byte protocol and write byte protocol.
5. The first send byte for write word protocol.
6. The first send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 1 – Index E1h
Bit
Name
R/W Reset Default
Description
TSI_TEMP1
R 5VSB
This is the high byte of Intel temperature interface PCH reading. The
- range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
This byte is used as multi-purpose:
7-0
1. The second received byte of read word protocol.
I2C_DATA1
2. The 11^th received byte of read block protocol.
R/W 5VSB 8’h00
3. The second send byte for write word protocol.
4. The second send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
49
Dec, 2011
V0.12P