F81867 Datasheet, PDF (251/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

1-0 FAN1_TEMP_SEL R/W 5VSB
F81867
This registers company with FAN1_TEMP_SEL_DIG select the
temperature source for controlling FAN1. The following value is
comprised by {FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL}
000: fan1 follows PECI temperature (CR7Eh)
001: fan1 follows temperature 1 (CR72h).
010: fan1 follows temperature 2 (CR74h).
01
011: fan1 follows temperature 0 (CR70h).
100: fan1 follows IBX/TSI CPU temperature (CR7Ah)
101: fan1 follows IBX PCH temperature (CR7Bh).
110: fan1 follows IBX MCH temperature (CR7Ch).
111: fan1 follows IBX maximum temperature (CR7Dh).
Others are reserved.
E. FAN2 Offset B0h~BFh
Address Attribute
Reset Default Value
Description
FAN2 count reading (MSB). At the moment of reading this register,
B0h
RO
3VCC
8’h0f
the LSB will be latched. This will prevent from data updating when
reading. To read the fan count correctly, read MSB first and
followed read the LSB.
B1h
RO
3VCC
8’hff
FAN2 count reading (LSB).
RPM mode(CR96 bit2=0):
B2h
R/W
VBAT
8’h00
FAN2 expect speed count value (MSB), in auto fan mode(CR96
bit3Î0) this register is auto updated by hardware.
Duty mode(CR96 bit2=1):
This byte is reserved byte.
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (LSB) or expect PWM duty , in
auto fan mode this register is auto updated by hardware and read
only.
B3h
R/W
VBAT
8’h01 Duty mode(CR96 bit2=1):
The Value programming in this byte is duty value. In auto fan
mode(CR96 bit3Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 ( 100%
251
Dec, 2011
V0.12P