F81867 Datasheet, PDF (224/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

3-0 I2C_PROTOCOL R/W 5VSB
F81867
Select what protocol if a I2C transfer is triggered.
0001b: send byte.
0010b: write byte.
0011b: write word.
0100b: Reserved.
0101b: block write.
0 0111b: quick command (write).
1001b: receive byte.
1010b: read byte.
1011b: Reserved
1101b: block read.
1111b: Reserved
Otherwise: reserved.
7.18.8.2 PECI 3.0 & Temperature Setting
PECI 3.0 Command and Register
PECI Configuration Register ⎯ Offset 40h
Bit
Name
R/W
7
RDIAMSR_CMD_E
N
R/W
6 C3_UPDATE_EN R/W
5-4
Reserved
R
3 C3_PTEMP_EN R/W
2 C0_PTEMP_EN R/W
1 C3_ALL0_EN R/W
0 C0_ALL0_EN R/W
Reset
5VSB
5VSB
-
5VSB
5VSB
5VSB
5VSB
Default
Description
When PECI temperature monitoring is enabled, set this bit 1 will
0 generate a RdIAMSR() command before a GetTemp()
command.
If RDIAMSR_CMD_EN is not set to 1, the temperature data is
0 not allowed to be updated when the completion code of
RdIAMSR() is 0x82.
- Reserved
0
Set this bit 1 to enable updateing positive value of temperature if
the completion code of RdIAMSR() is 0x82.
Set this bit 1 to enable updating positive value of temperature if
0 the completion code of RdIAMSR() is not 0x82 and the bit 8 of
completion code is not 1 either.
0
Set this bit 1 to enable updating temperature value 0x0000 if the
completion code of RdIAMSR() is 0x82.
Set this bit 1 to enable updating temperature value 0x0000 if the
0 completion code of RdIAMSR() is not 0x82 and the bit 8 of
completion code is not 1 either.
PECI Master Control Register ⎯ Offset 41h
Bit
Name
R/W
7
PECI_CMD_STAR
T
W
6-5
Reserved
R
Reset
5VSB
-
Default
Description
-
Write 1 to this bit to start a PECI command when using as a PECI
master. (PECI_PENDING must be set to 1)
- Reserved
4 PECI_PENDING R/W 5VSB
0 Set this bit 1 to stop monitoring PECI temperature.
3
Reserved
R
-
- Reserved
224
Dec, 2011
V0.12P