F81867 Datasheet, PDF (286/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
PS/2 Reset Control Register ⎯ Offset 0Bh
Bit
Name
R/W Reset Default
Description
7-6
Reserved
-
-
- Reserved.
5
LRESET_ST
R 5VSB 0 The status of LRESET#.
4
KBC_S3
R 5VSB 0 The S3 condition status for PS/2.
3-2
Reserved
-
-
- Reserved.
1
μC_LRESET_N R/W 5VSB 1 When PS2_CTRL_EN is set, μC could use the bit to reset KBC block.
0
μC_KBC_S3
R/W 5VSB
0
When PS2_CTRL_EN is set, μC could use the bit to emulate a S3 condition
for wakeup function.
PS/2 Reset Control Register ⎯ Offset 0Ch
Bit
Name
R/W Reset Default
Description
7
P_MDATA_IN
R
-
- Pin status of MDATA.
6
P_MCLK_IN
R
-
- Pin status of MCLK.
5
P_KDATA_IN
R
-
- Pin status of KDATA.
4
P_KCLK_IN
R
-
- Pin status of KCLK.
3 μC_MDATA_OUT R/W 5VSB 1 When μC_MO_PIN_EN is set, μC uses this bit to control the MDATA.
2
μC_MCLK_OUT R/W 5VSB
1 When μC_MO_PIN_EN is set, μC uses this bit to control the MCLK.
1 μC_KDATA_OUT R/W 5VSB 1 When μC_KB_PIN_EN is set, μC uses this bit to control the KDATA.
0
μC_KCLK_OUT R/W 5VSB 1 When μC_KB_PIN_EN is set, μC uses this bit to control the KCLK.
PS/2 Control Register ⎯ Offset 0Fh
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3
μC_KB_PIN_EN R/W 5VSB
0 ^{Set “1” to control KCLK/KDATA by μC_KCLK_OUT and μC_KDATA_OUT.}
2 μC_MO_PIN_EN R/W 5VSB 0 ^{Set “1” to control MCLK/MDATA by μC_MCLK_OUT and μC_MDATA_OUT.}
1
PS2_CTRL_EN R/W 5VSB
0 PSEUDO_8048_EN R/W 5VSB
0: Disable μC to control PS/2 interface.
0 1: Enable μC to control PS/2 interface. μC could assert read/write signal to
PS/2 block if PSEUDO_8048_EN is “0”.
Set “1” to emulate 8048 to response KBC command. When this bit is set, any
0 read/write signal for PS/2 is block. μC is responsible to return the data to
keyboard controller.
7.20.12 ACPI μC Side Register (Base Address 0x2300, 256 bytes)
ACPI Pin Status 1 Register ⎯ Offset 03h
Bit
Name
R/W Reset Default
7
Reserved
-
-
- Reserved.
6
RSMRST_N_IN
R
-
0 ^{Pin status of RSMRST#.}
5
PWROK_IN
R
-
0 ^{Pin status of PWROK.}
4
PSON_N_IN
R
-
0 ^{Pin status of PS_ON#.}
3
PWSOUT_N_IN
R
-
0 ^{Pin status of PWSOUT#.}
Description
286
Dec, 2011
V0.12P