F81867 Datasheet, PDF (273/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
0: Disable SMI event.
1 GPIO51_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO51_SMI_ST is set.
0: Disable SMI event.
0 GPIO50_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO50_SMI_ST is set.
GPIO5 SMI Status Register ⎯ offset A9h
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7 GPIO57_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO57 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
6 GPIO56_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO56 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
5 GPIO55_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO55 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
4 GPIO54_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO54 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
3 GPIO53_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO53 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
2 GPIO52_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO52 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1 GPIO51_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO51 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
0 GPIO50_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO50 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
GPIO6 Output Enable Register ⎯ offset 90h
Bit
Name
R/W Reset Default
Description
0: GPIO67 is in input mode.
7
GPIO67_OE
R/W LRESET# 0
1: GPIO67 is in output mode.
0: GPIO66 is in input mode.
6
GPIO66_OE
R/W LRESET# 0
1: GPIO65 is in output mode.
0: GPIO65 is in input mode.
5
GPIO65_OE
R/W LRESET# 0
1: GPIO65 is in output mode.
0: GPIO64 is in input mode.
4
GPIO64_OE
R/W LRESET# 0
1: GPIO64 is in output mode.
0: GPIO63 is in input mode.
3
GPIO63_OE
R/W LRESET# 0
1: GPIO63 is in output mode.
0: GPIO62 is in input mode.
2
GPIO62_OE
R/W LRESET# 0
1: GPIO62 is in output mode.
273
Dec, 2011
V0.12P