F81867 Datasheet, PDF (291/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
Port Select Register ⎯ offset 27h
Bit
Name
R/W Reset Default
Description
0: Enable OVP function.
7
OVP_MODE R/W VBAT* - 1: Default is disabled; internal pull high 47k Ω .
The default value is determined by power on strap.
0: ATX Mode.
6
AT_MODE
R/W 5VSB - 1: AT Mode.
The default value is determined by power on strap.
5 GPIO_DEC_RANGE R/W 3VCC
0 0: The GPIO I/O space is 8-byte.
1: The GPIO I/O space is 16-byte.
- 0: The configuration register port is 2E/2F.
4
PORT_4E_EN R/W 5VSB*
1: The configuration register port is 4E/4F.
This register is power on trapped by RTS1#/ Config4E_2E. Pull down to
select port 2E/2F. This bit is accessed by host side only.
3-2 GPIO_PROG_SEL R/W 5VSB
Offset 2Ch register select.
00: GPIO0_EN
01: GPIO1_EN
10: GPIO2_EN
0
11: μC_PORT_EN.
Bit 0 also select the offset 28h register:
0: Multi-function Select 1 Register
1: Multi-function Select 2 Register.
1
Reserved
-
-
- Reserved
0
CLK_TUNE_PROG_
EN
R/W
3VCC
0 Set “1” to enable index 0x29, 0x2a, 0x2b, 0x2c function as clock fine tune
register.
Multi-function Select 1 Register ⎯ offset 28h (Available when GPIO_PROG_SEL[0] = 0)
Bit
Name
R/W _Reset Default
Description
7
Reserved
-
-
- Reserved
Pin 9 ~ 21 function select.
6
FDC_GP_EN
R/W 5VSB
1 ^{These pins are controlled by FDC_GP_EN, UART5_FUNC_SEL,}
UART6_FUNC_SEL and PWM_PIN_EN.
To function as FDC, all these bits should be clear to “0”.
Pin 102 ~ 118 function select.
5
LPT_GP_EN
R/W 5VSB
1 0: Functions as parallel port.
1: Functions as GPIO7/GPIO8.
Pin 61, 62 function select.
4
MO_I2C_EN
R/W 5VSB 0 0: PS/2 mouse interface MCLK/MDATA.
1: I2C SCL/SDA.
291
Dec, 2011
V0.12P