F81867 Datasheet, PDF (227/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
PECI Master DATA11 Register ⎯ Offset 4Eh
Bit
Name
R/W Reset Default
Description
7-0 PECI_DATA11 R/W 5VSB
0 For RdIAMSR(), this byte represents “DATA[55:48]”.
PECI Master DATA12 Register ⎯ Offset 4Fh
Bit
Name
R/W Reset Default
Description
7-0 PECI_DATA12 R/W 5VSB
0 For RdIAMSR(), this byte represents “DATA[63:56]”.
HM Manual Control Register1 ⎯ Offset 50h
Bit
Name
R/W Reset Default
Description
7
LOAD_CH
W
-
- Write 1 to load a temperature or voltage channel to be converted
6
STOP_CH
R/W 5VSB
0
Set to 1 when load a channel will generate a one-shot
conversion.
5
HOLD_CH
R/W 5VSB
0 Set to 1 when load a channel will keep converting this channel.
First channel to be converted when LOAD_CH is set to 1.
00000: VCC
00001: VIN1
00010: VIN2
00011: VIN3
00100: VIN4
4:0
CHANNEL
R/W 5VSB
0 00101: VSB3V
00110: VBAT
00111: VSB5V
10000: Intel PECI
10001: T1
10010: T2
11000: AMD TSI/Intel IBex
HM Manual Control Status Register 1⎯ Offset 51h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved
6 V_CONV_STS R 5VSB
- At least one of the voltage channels had finish converting.
5 PECI_CONV_STS WC 5VSB
- PECI channel had finish converting
4 TSI_CONV_STS WC 5VSB
- TSI channel had finish converting
3
Reserved
-
- Reserved
2
T2_CONV_STS WC 5VSB
- T2 channel had finish converting
1
T1_CONV_STS WC 5VSB
- T1 channel had finish converting
0
Reserved
-
- Reserved
HM Manual Control Status Register 2⎯ Offset 52h
Bit
Name
R/W Reset Default
Description
7 VSB5V_CONV_STS WC 5VSB
- VSB5V voltage channel had finish converting
6 VBAT_CONV_STS WC
5
VSB3V_CONV_ST
S
WC
5VSB
5VSB
- VBAT voltage channel had finish converting
- VSB3V voltage channel had finish converting
227
Dec, 2011
V0.12P