F81867 Datasheet, PDF (142/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7.7 GPIO Registers (CR06)
7.7.1 GPIO Configuration Registers
“-“ Reserved or Tri-State
Register
0x[HEX]
30
Register Name
GPIO Device Enable Register
60
Base Address High Register
61
Base Address Low Register
F81867
MSB
Default Value
LSB
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
GPIO Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable GPIO I/O port.
0
GPIO_EN
R/W LRESET# 0
1: enable GPIO I/O port.
Description
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 GP_BASE_ADDR_HI R/W LRESET# 00h The MSB of GPIO I/O port address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
The LSB of KBC data port address. When GPIO_DEC_RANGE is “0”, only 8
bytes are decoded:
Base + 0: index port.
Base + 1: data port.
Base + 2: GPIO8 data register.
Base + 3: GPIO7 data register.
Base + 4: GPIO6 data register.
Base + 5: GPIO5 data register.
Base + 6: GPIO0 data register.
Base + 7: GPIO1 data register.
If GPIO_DEC_RANGE is set to “1”, more 8 bytes are decoded:
7-0 BASE_ADDR_LO R/W LRESET# 60h _{Base + 8: GPIO2 data register.}
Base + 9: GPIO3 data register.
Base + 10: GPIO4 data register.
Otherwise: Reserved.
There are three ways to access the GPIO registers.
1. Use configuration register port 0x4E/0x4F (or 0x2E/0x2F), the LDN for
GPIO is 0x06.
2. Use GPIO index/data port. Write index to index port first and then
read/write the register.
3. Use digital I/O port. The way only access GPIO data register. Write data to
this port will control the data output register. And read this port will read the
pin status register.
142
Dec, 2011
V0.12P