F81867 Datasheet, PDF (153/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
0: Disable SMI event.
5 GPIO15_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO15_SMI_ST is set.
0: Disable SMI event.
4 GPIO14_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO14_SMI_ST is set.
0: Disable SMI event.
3 GPIO13_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO13_SMI_ST is set.
0: Disable SMI event.
2 GPIO12_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO12_SMI_ST is set.
0: Disable SMI event.
1 GPIO11_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO11_SMI_ST is set.
0: Disable SMI event.
0 GPIO10_SMI_EN R/W 5VSB 0
1: Enable SMI event via PME# or SIRQ if GPIO10_SMI_ST is set.
GPIO1 SMI Status Register ⎯ Index E9h
Bit
Name
R/W Reset Default
Description
0: No SMI event.
7 GPIO17_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO17 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
6 GPIO16_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO16 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
5 GPIO15_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO15 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
4 GPIO14_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO14 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
3 GPIO13_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO13 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
2 GPIO12_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO12 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
1 GPIO11_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO11 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
0 GPIO10_SMI_ST R/W 5VSB 0 1: A SMI event will set if GPIO10 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
153
Dec, 2011
V0.12P