F81867 Datasheet, PDF (211/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

4 RTC_WR_DIS_4 R/W _5VSB
3 RTC_WR_DIS_3 R/W _5VSB
2 RTC_WR_DIS_2 R/W _5VSB
1 RTC_WR_DIS_1 R/W 5VSB
0 RTC_WR_DIS_0 R/W 5VSB
Set “1” to enable write protect for RTC RAM index
0
0xC0 ~ 0xCF.
Set “1” to enable write protect for RTC RAM index
0
0xB0 ~ 0xBF.
Set “1” to enable write protect for RTC RAM index
0
0xA0 ~ 0xAF.
Set “1” to enable write protect for RTC RAM index
0
0x90 ~ 0x9F.
Set “1” to enable write protect for RTC RAM index
0
0x80 ~ 0x8F.
Software Reset 1 Register ⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
7
RSMFI
W
-
- Write “1” to assert a software reset to SPI block.
6-5
Reserved
-
-
- Reserved.
4
RINTC
W
-
- Write “1” to assert a software reset to INTC block.
3-2
Reserved
-
-
- Reserved.
1
RCIR
W
-
- Write “1” to assert a software reset to CIR block.
0
RPWM
W
-
- Write “1” to assert a software reset to PWM block.
Software Reset 2 Register ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3 ACPI_WD_RST_DIS R/W 5VSB
0: ACPI will reset by μC watchdog timeout.
1
1: ACPI won’t be reset by μC watchdog timeout.
2 KBC_WD_RST_DIS R/W 5VSB
0: KBC will reset by μC watchdog timeout.
1
1: KBC won’t be reset by μC watchdog timeout.
1 GPIO_WD_RST_DIS R/W 5VSB
0: GPIO will reset by μC watchdog timeout.
1
1: GPIO won’t be reset by μC watchdog timeout.
0 CFG_WD_RST_DIS R/W 5VSB
0: CFG will reset by μC watchdog timeout.
1
1: CFG won’t be reset by μC watchdog timeout.
Software Reset 2 Register ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3
RACPI
W 5VSB - Write “1” to assert a software reset to ACPI block.
2
RKBC
W 5VSB - Write “1” to assert a software reset to KBC block.
1
RGPIO
W 5VSB - Write “1” to assert a software reset to GPIO block.
0
RCFG
W 5VSB - Write “1” to assert a software reset to CFG block.
F81867
211
Dec, 2011
V0.12P