F81867 Datasheet, PDF (7/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
Commands ..................................................................................................................................... 87
PS/2 wakeup function..................................................................................................................... 89
6.6 GPIO ...................................................................................................................................... 89
6.6.1
GPIO Access Method ..................................................................................... 89
6.6.2
GPIOx status .................................................................................................. 91
6.7 Watchdog Timer Function ...................................................................................................... 94
6.8 ACPI Function ........................................................................................................................ 95
6.8.1Power Control........................................................................................................... 96
6.8.1.1Wake Up Via Sleep State .................................................................................................... 96
6.8.1.2Wake Up Stage Detection ................................................................................................... 96
6.8.1.3AC Loss & Resume Control Methods.................................................................................. 97
6.8.2Intel Power Saving Function Deep Sleep Well (DSW) ............................................. 98
6.8.3Power Saving Controller (Fintek ERP Mode) ......................................................... 100
6.8.4ACPI Timing ........................................................................................................... 104
6.8.4.1G3 To S0............................................................................................................................ 104
6.8.4.2G3 To S0 (only DSW) ........................................................................................................ 105
6.8.4.3G3 To S0 (DSW & ERP, AC Resume Green Bold Line) .................................................... 106
6.8.4.4DSW To S0 ........................................................................................................................ 107
6.8.4.5S0 to DSW......................................................................................................................... 108
6.8.4.6S0 to G3’ ........................................................................................................................... 109
6.9 UART ................................................................................................................................... 110
6.10 AMD TSI and Intel PECI 3.0 Functions ................................................................................ 114
6.11 Over Voltage Protection ....................................................................................................... 116
6.12 Microcontroller...................................................................................................................... 116
6.13 Debug Port Function ............................................................................................................ 116
6.14 H2E Function ....................................................................................................................... 117
7. Register Description ................................................................................................... 119
7.1 Global Control Registers ...................................................................................................... 120
7.2 Multifunction Function Register Mapping Table ................................................................... 128
7.2.1
Multi Function Register Mapping For FDC ................................................... 128
7.2.2
Multi Function Register Mapping For Parallel Port (LPT) ............................. 129
7.2.3
Multi Function Register Mapping For Hardware Monitor .............................. 129
7.2.4
Multi Function Register Mapping For KBC (PS/2 Mouse)............................. 130
7.2.5
Multi Function Register Mapping For GPIO0x .............................................. 130
7.2.6
Multi Function Register Mapping For GPIO1x .............................................. 130
7.2.7
Multi Function Register Mapping For GPIO2x .............................................. 131
7.2.8
Multi Function Register Mapping For GPIO3x .............................................. 131
Dec, 2011
V0.12P