F81867 Datasheet, PDF (246/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
FAN PROGRAMMABLE DUTY-CYCLE/VOLTAGE LOADED AFTER POWER-ON ⎯ Offset 9Eh
Bit
Name
R/W Reset Default
Description
This byte will be immediately loaded as Fan duty value after
7-0 PROG_DUTY_VAL R/W 5VSB 66h VDD is powered on if it has been programmed before shut
down.
Fan Fault Time Register ⎯ Offset 9Fh
Bit
Name
R/W Reset Default
Description
7 FAN_PROG_SEL R/W 5VSB
0 Set this bit to “1” will enable accessing registers of other bank.
6 FAN_MNT_SEL R/W 5VSB
0 ^{Set this bit to monitor a slower fan.}
5
Reserved
-
-
- Reserved
4 FULL_DUTY_SEL R/W 3VCC
3-0 F_FAULT_TIME R/W 5VSB
0: The Fan Duty is 100% and will be loaded immediately after
VDD is powered on if CR9E is not been programmed before
shut down. (pull down by external resistor)
- 1: The Fan Duty is 40% and will be loaded immediately after
VDD is powered on if CR9E is not been programmed before
shut down. (pull up by internal 47K Ω resistor).
This register is power on trap by DTR1#.
This register determines the time of fan fault. The condition to
cause fan fault event is:
When PWM_Duty reaches FFh, if the fan speed count can’t
reach the fan expect count in time.
The unit of this register is 1 second. The default value is 11
Ah seconds.
(Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
Another condition to cause fan fault event is fan stop and the
PWM duty is greater than the minimum duty programmed by
the register Offset 9C-9Dh.
246
Dec, 2011
V0.12P