F81867 Datasheet, PDF (11/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
¾ 8032 embedded microprocessor
¾ Support WDT Reset Function
¾ Support WDT wake up while ERP function is enabled
¾ Provide 4 sets of GPIO (GPIO0x/1x/5x/8x) SMI event via PME# or SIRQ
¾ Provide different SIRQ channels for GPIO0x/1x/5x/8x
¾ Support portable remote control via CIR RC6
¾ Provide one FDC, KBC and Parallel Port
¾ Provide 6 fully functional UART and 1 SIR
9 Programmable 16/32/64/128 bytes FIFO
9 Multi drop function & 128 Bytes for UARTs
9 Support IRQ Sharing function.
9 Provide auto flow control function
¾ H/W monitor functions
9 Support OVP & UVP for 3VCC and VIN2&3
9 Support smart fan FQST for FAN 1
9 Support PECI 3.0
9 Support IBX PCH temperature reading via I2C
9 Support AMD TSI
¾ 72 GPIO Pins for flexible application
¾ Provide 16 bytes Serial ID
¾ Support LED blinking function
¾ Provide Power Saving Function (Comply ERP lot 6.0)
¾ Support Intel Deep Sleep Well (DSW) Timing Sequence
¾ Provide wake-up events via power button, GPIO0x, GPIO1x, RI1#, and RI2#
¾ Provide ATX emulates AT function
¾ 14.318/24/48 MHz clock input
¾ Packaged in 128-LQFP
FDC
¾ Compatible with IBM PC AT disk drive systems
¾ Variable write pre-compensation with track selectable capability
¾ Support vertical recording format
¾ DMA enable logic
¾ 16-byte data FIFOs
¾ Support floppy disk drives and tape drives
¾ Detects all overrun and under run conditions
¾ Built-in address mark detection circuit to simplify the read electronics
¾ Completely compatible with industry standard 82077
¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
11
Dec, 2011
V0.12P