F81867 Datasheet, PDF (18/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

5.2 Clock
Pin
Pin Name
32
PCICLK
33
CLKIN
F81867
Type
IN_st
IN_st
PWR
3VCC
3VCC
Description
33MHz PCI clock input.
System clock input. According to the input frequency
14.318/24/48MHz (default 48MHz).
5.3 LPC Interface
Pin
Pin Name
Type
23
LRESET#
24
LDRQ#
25
SERIRQ
26
LFRAME#
IN_st
O₁₆
I/O_16st
IN_st
27-30
32
33
LAD[0:3]
PCICLK
CLKIN
I/O_16st
IN_st
IN_st
PWR
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
Description
Reset signal. It can connect to PCIRST# signal on
the host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a
broken cycle.
These signal lines communicate address, control,
and data information over the LPC bus between a
host and a peripheral.
33MHz PCI clock input.
System clock input. According to the input frequency
14.318/24/48MHz (default 48MHz).
5.4 FDC
Pin No.
Pin Name
GPIO50
DENSEL#
9
RTS6#
GPIO51
10
MOA#
SIN6
GPIO52
DRVA#
11
SOUT6
GPIO53
12
WDATA#
Type
I/OOD_{14st, 5v}
OD_14,5v
O₁₄
I/OOD_{14st, 5v}
OD_14,5v
IN_st,5v
I/OOD_{14st, 5v}
OD_14,5v
O₁₄
I/OOD_{14st, 5v}
OD_14,5v
PWR
3VCC
3VCC
3VCC
3VCC
Description
General Purpose IO.
Drive Density Select.
Set to 1 – High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
UART Request To Send. An active low signal informs
the modem or data set that the controller is ready to
send data.
General Purpose IO.
Motor A On. When set to 0, this pin enables disk
drive 0. This is an open drain output.
UART Serial Input. Used to receive serial data
through the communication link.
General Purpose IO.
Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
UART Serial Output. Used to transmit serial data
out to the communication link.
General Purpose IO.
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD.
18
Dec, 2011
V0.12P