F81867 Datasheet, PDF (181/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
ACPI Control Register 3 ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
Select the KBC S3 condition source.
7
S3_SEL
R/W 5VSB 0 0: Enter S3 state when internal VDD3VOK signal de-asserted.
1: Enter S3 state when S3# is low or the TS3 register is set to 1.
6-5
Reserved
- 5VSB - Reserved.
0: PSON# is the inverted of S3# signal.
4
PSON_DEL_EN R/W 5VSB
0 1: PSON# will sink low only if the time after the last turn-off elapse at least 4
seconds.
3 WDT_PWROK_EN R/W 5VSB 0 Set “1” to this bit will enable WDT timeout event asset from PWROK pin.
2-0
Reserved
-
- Reserved.
LED Control Register 1 ⎯ Index F8h
Bit
Name
R/W _Reset Default
Description
7 _{LED_VCC_INV_DIS R/W VBAT}
6
LED_VCC_DS3 R/W VBAT
5-4 _{LED_VCC_S5_MODE R/W VBAT}
3-2 _{LED_VCC_S3_MODE R/W VBAT}
0: LED_VCC clock output is inverted.
0
1: LED_VCC clock output is not inverted.
0: Disable LED_VCC deep S3 mode.
0
1: Enable LED_VCC deep S3 mode. Output 75% duty 0.25HZ clock.
The three bits {LED_VCC_S5_MODE_ADD, LED_VCC_S5_MODE [1:0]}
select the LED_VCC mode in S5 state.
000: Sink low.
001: Tri-state or drive high control by GPIO11_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
*When LED_VCC_INV_DIS is set to “1” the duty is 25%, otherwise, the duty
is 75%.
The three bits {LED_VCC_S3_MODE_ADD, LED_VCC_S3_MODE [1:0]}
select the LED_VCC mode in S3 state.
000: Sink low.
001: Tri-state or drive high control by GPIO11_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
*When LED_VCC_INV_DIS is set to “1” the duty is 25%, otherwise, the duty
is 75%.
181
Dec, 2011
V0.12P