F81867 Datasheet, PDF (145/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
GPIO0 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
1-0 GP0_IRQ_MODE R/W LRESET# 0 10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP0_IRQ_SHARE is “1”).
7.7.4 GPIO0x Configuration Registers
Register
0x[HEX]
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
Register Name
GPIO0 Output Enable Register
GPIO0 Output Data Register
GPIO0 Pin Status Register
GPIO0 Drive Enable Register
GPIO0 Output Mode 1 Register
GPIO0 Output Mode 2 Register
GPIO0 Pulse Width Select 1 Register
GPIO0 Pulse Width Select 2 Register
GPIO0 SMI Enable Register
GPIO0 SMI Status Register
MSB
Default Value
LSB
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO0 Output Enable Register ⎯ Index F0h
Bit
Name
R/W Reset Default
0: GPIO07 is input.
7
GPIO07_OE
R/W 5VSB 0
1: GPIO07 is output.
0: GPIO06 is input.
6
GPIO06_OE
R/W 5VSB 0
1: GPIO06 is output.
0: GPIO05 is input.
5
GPIO05_OE
R/W 5VSB 0
1: GPIO05 is output.
0: GPIO04 is input.
4
GPIO04_OE
R/W 5VSB 0
1: GPIO04 is output.
0: GPIO03 is input.
3
GPIO03_OE
R/W 5VSB 0
1: GPIO03 is output.
0: GPIO02 is input.
2
GPIO02_OE
R/W 5VSB 0
1: GPIO02 is output.
0: GPIO01 is input.
1
GPIO01_OE
R/W 5VSB 0
1: GPIO01 is output.
Description
145
Dec, 2011
V0.12P