F81867 Datasheet, PDF (213/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

00: PWM1 clock source is group 0 clock.
01: PWM1 clock source is group 1 clock.
3-2
PCS1
R/W 5VSB 00
10: PWM1 clock source is group 2 clock.
11: PWM1 clock source is group 3 clock.
00: PWM0 clock source is group 0 clock.
01: PWM0 clock source is group 1 clock.
1-0
PCS0
R/W 5VSB 00
10: PWM0 clock source is group 2 clock.
11: PWM0 clock source is group 3 clock.
F81867
PWM Clock Gate Register ⎯ Offset 08h
Bit
Name
R/W Reset Default
7-4
Reserved
-
-
- Reserved.
0: Enable PWM3 clock.
3
PCSGR3
R/W 5VSB 0
1: Disable PWM3 clock.
0: Enable PWM2 clock.
2
PCSGR2
R/W 5VSB 0
1: Disable PWM2 clock.
0: Enable PWM1 clock.
1
PCSGR1
R/W 5VSB 0
1: Disable PWM1 clock.
0: Enable PWM0 clock.
0
PCSGR0
R/W 5VSB 0
1: Disable PWM0 clock.
Description
PWM Type Register ⎯ Offset 09h
Bit
Name
R/W Reset Default
7-4
Reserved
-
-
- Reserved.
0: Open drain.
3
PWM3_TYPE R/W 5VSB 0
1: Push pull.
0: Open drain.
2
PWM2_TYPE R/W 5VSB 0
1: Push pull.
0: Open drain.
1
PWM1_TYPE R/W 5VSB 0
1: Push pull.
0: Open drain.
0
PWM0_TYPE R/W 5VSB 0
1: Push pull.
Description
PWM Enable Register ⎯ Offset 0Ah
Bit
Name
R/W Reset Default
Description
7
SOFT_RST
W 5VSB 0 Write “1” to software reset PWM block.
6-1
Reserved
-
-
- Reserved.
0: Disable PWM. All clocks will be disabled.
0
PCCE
R/W 5VSB 0
1: Enable PWM.
PWM0 Duty Control Register ⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
7-0
DCR0
R/W 5VSB
0
The duty cycle of PWM0 will be (DCR0/255)*100%. Set 0 to force stop and
0xFF to force 100% duty.
213
Dec, 2011
V0.12P