F81867 Datasheet, PDF (272/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

GPIO5 Pin Status Register ⎯ offset A2h
Bit
Name
R/W Reset Default
Description
4
GPIO57_IN
R
-
- The pin status of GPIO57/WGATE#/DSR6#/T2EX.
4
GPIO56_IN
R
-
- The pin status of GPIO56/HDSEL#/DTR6#/T2.
4
GPIO55_IN
R
-
- The pin status of GPIO55/STEP#/CTS6#/P35.
4
GPIO54_IN
R
-
- The pin status of GPIO54/DIR#/RI6#/P34.
3
GPIO53_IN
R
-
- The pin status of GPIO53/WDATA#/DCD6#/P33.
2
GPIO52_IN
R
-
- The pin status of GPIO52/DRVA#/SOUT6/P32.
1
GPIO51_IN
R
-
- The pin status of GPIO51/MOA#/SIN6/P31.
0
GPIO50_IN
R
-
- The pin status of GPIO50/DENSEL#/RTS6#/P30.
F81867
GPIO5 Drive Enable Register ⎯ offset A3h
Bit
Name
R/W Reset Default
Description
0: GPIO57 is open drain in output mode.
7 GPIO57_DRV_EN R/W LRESET# 0
1: GPIO57 is push pull in output mode.
0: GPIO56 is open drain in output mode.
6 GPIO56_DRV_EN R/W LRESET# 0
1: GPIO56 is push pull in output mode.
0: GPIO55 is open drain in output mode.
5 GPIO55_DRV_EN R/W LRESET# 0
1: GPIO55 is push pull in output mode.
0: GPIO54 is open drain in output mode.
4 GPIO54_DRV_EN R/W LRESET# 0
1: GPIO54 is push pull in output mode.
0: GPIO53 is open drain in output mode.
3 GPIO53_DRV_EN R/W LRESET# 0
1: GPIO53 is push pull in output mode.
0: GPIO52 is open drain in output mode.
2 GPIO52_DRV_EN R/W LRESET# 0
1: GPIO52 is push pull in output mode.
0: GPIO51 is open drain in output mode.
1 GPIO51_DRV_EN R/W LRESET# 0
1: GPIO51 is push pull in output mode.
0: GPIO50 is open drain in output mode.
0 GPIO50_DRV_EN R/W LRESET# 0
1: GPIO50 is push pull in output mode.
GPIO5 SMI Enable Register ⎯ offset A8h
Bit
Name
R/W Reset Default
Description
0: Disable SMI event.
7 GPIO57_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO57_SMI_ST is set.
0: Disable SMI event.
6 GPIO56_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO56_SMI_ST is set.
0: Disable SMI event.
5 GPIO55_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO55_SMI_ST is set.
0: Disable SMI event.
4 GPIO54_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO54_SMI_ST is set.
0: Disable SMI event.
3 GPIO53_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO53_SMI_ST is set.
0: Disable SMI event.
2 GPIO52_SMI_EN R/W LRESET# 0
1: Enable SMI event via PME# or SIRQ if GPIO52_SMI_ST is set.
272
Dec, 2011
V0.12P