F81867 Datasheet, PDF (29/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

6. Function Description
F81867
6.1 Power on Strapping Option
The F81867 provides eight pins for power on hardware strapping to select required functions. See
below table for the detail:
Pin No.
4
Symbol
OVP_Mode
69
ATX_AT_TRAP
99
PWM_DAC1
101
PWM_DAC2
103
PWM_DAC3
123
FAN40_100
124
Config4E_2E
126
I2C_ADDR
Value
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Description
Disable (default): internal pull high 47k Ω . Voltage
protection function is enabled via setting the related
registers.
Enable OVP function.
ATX mode (default, internal pull high 47k Ω ).
AT mode.
PWM mode.
DAC mode (default, internal pull down 100k Ω )
PWM mode.
DAC mode (default, internal pull down 100k Ω )
PWM mode.
DAC mode (default, internal pull down 100k Ω )
Power on fan speed default duty is 40%. ( Default)
Power on fan speed default duty is 100%.
Configuration Register I/O port is 4E/4F. (Default)
Configuration Register I/O port is 2E/2F.
The I2C slave address is 0X5C (Default)
The I2C slave address is 0X5A
6.2 FDC
The Floppy Disk Controller provides the interface between a host processor and one floppy disk drive. It
integrates a controller and a digital data separator with write pre-compensation, data rate selection logic,
microprocessor interface, and a set of registers. The FDC supports data transfer rates of 250 Kbps, 300 Kbps,
500 Kbps, 1 Mbps and 2 Mbps. It operates in PC/AT mode.
The FDC configuration is handled by software and a set of Configuration registers. Status, Data, and
Control registers facilitate the interface between the host microprocessor and the disk drive, providing
information about the condition and/or state of the FDC. These configuration registers can select the data rate,
enable interrupts, drives, and DMA modes, and indicate errors in the data or operation of the FDC/FDD.
29
Dec, 2011
V0.12P