F81867 Datasheet, PDF (288/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
KB PME Control Register ⎯ Offset 0Eh
Bit
Name
R/W Reset Default
Description
7-6
Reserved
- 5VSB - Reserved.
5
MS_PME_ST R/WC 5VSB
-
This bit is the status of mouse PME event. It is the same as the PME
configuration register in host side. Write “1” will clear the status.
4
KB_PME_ST R/WC 5VSB
- ^{This bit is the status of keyboard PME event. It is the same as the PME}
configuration register in host side. Write “1” will clear the status.
3-2
Reserved
- 5VSB - Reserved.
0: Disable mouse PME event.
1
MS_PME_EN R/W 5VSB 0
1: Enable mouse PME event.
0: Disable keyboard PME event.
0
KB_PME_EN R/W 5VSB 0
1: Enable keyboard PME event.
ERP State Control Register ⎯ Offset 0Fh
Bit
Name
R/W Reset Default
Description
7
S3_BACK
R/W 5VSB 0 μC set this bit to inform host that the system is return from deep S3 state.
6-2
Reserved
-
-
- ^Reserved.
0
DS3_STATE
R/W 5VSB
μC set this bit to make ACPI control signals entering deep S3 state. For
0 _{example, LED will output 0.25Hz clock in deep S3 state.}
ACPI Deep S3 Control Register ⎯ Offset 0Fh
Bit
Name
R/W Reset Default
Description
7
S3_BACK
R/W 5VSB 0 Set “1” to inform host the system is back from S3 state.
6-1
Reserved
-
-
- ^Reserved.
0
DS3_STATE
R/W 5VSB 0 ^{Set “1” to enter deep S3 state.}
ACPI Interrupt Enable Register 1⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
7
LRESET_ST_INT_E
N
R/W
5VSB
0: Disable LRESET# pin status interrupt.
0 1: Enable LRESET# pin status interrupt. An interrupt will assert to μC if
LRESET# pin status change.
0: Disable S5 state interrupt.
6
S5_ST_INT_EN R/W 5VSB 0 1: Enable S5 state interrupt. An interrupt will assert to μC if system enter S5
state.
0: Disable S3 state interrupt.
5
S3_ST_INT_EN R/W 5VSB 0 1: Enable S3 state interrupt. An interrupt will assert to μC if system enter S3
state.
0: Disable S0 state interrupt.
4
S0_ST_INT_EN R/W 5VSB 0 1: Enable S0 state interrupt. An interrupt will assert to μC if system enter S0
state.
0: Disable S5# pin status interrupt.
3
S5_INT_EN
R/W 5VSB 0 1: Enable S5# pin status interrupt. An interrupt will assert to μC if S5# pin
status change.
0: Disable S3# pin status interrupt.
2
S3_INT_EN
R/W 5VSB 0 1: Enable S3# pin status interrupt. An interrupt will assert to μC if S3# pin
status change.
288
Dec, 2011
V0.12P