F81867 Datasheet, PDF (189/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
6-1
Reserved
- 5VSB - Reserved
Set “!” to enable debug port. Debug port register could be accessed by set
address to 0x3200 + offset. To access the μC side register including SFR
0
DBPORT_EN
R/W 5VSB
0 _{and RAM data. Entry key should be entered via the debug port μC side}
register.
Debug Port Control Register ⎯ Offset + 0x01
Bit
Name
R/W Reset Default
Description
7 BRK_PRT_TRIG R 5VSB 0 Status of breakpoint trigger.
6-1
Reserved
-
-
- Reserved
Set “!” to enable debug port. Debug port register could be accessed by set
0
DBPORT_EN R/W 5VSB 0 address to 0x3200 + offset. To access the μC side register including SFR
and RAM data. Entry key should be entered via debug port μC side register.
Debug Port Address Low Byte Register ⎯ Offset + 0x04
Bit
Name
R/W Reset Default
Description
7-0 DBPORT_L_ADDR R/W 5VSB 0 Address low byte for μC side register address.
Debug Port Address High Byte Register ⎯ Offset + 0x05
Bit
Name
R/W Reset Default
Description
7-0 DBPORT_H_ADDR R/W 5VSB 0 Address high byte for μC side register address.
7.14 UART1 Registers (CR10)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
Device Enable Register
60
Base Address High Register
61
Base Address Low Register
70
IRQ Channel Select Register
F0
IRQ Share Register
F2
Clock Select Register
F4
9bit-mode Slave Address Register
F5
9bit-mode Slave Address Mask Register
F6
FIFO Mode Register
MSB
--
00
11
--
00
--
00
00
00
Default Value
----
0000
1110
- - 01
00 - -
----
0000
0000
000 -
LSB
-1
11
00
00
00
00
00
00
00
UART 1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
- Reserved
0: disable UART 1 I/O Port.
0
UART 1_EN
R/W LRESET# 1
1: enable UART 1 I/O Port.
189
Dec, 2011
V0.12P