F81867 Datasheet, PDF (96/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
Control Signal
RSMRST#
S3#
S5#
PWSIN#
PWSOUT#
ATXPG_IN
PS_ON#
PWOK
PME#
PS/2 KB/MS
RI1#/RI2#
GPIO0x/GPIO1x
SLP_SUS#
SUS_ACK#
SUS_WARN#
ERP_CTRL0#
ERP_CTRL1#
◇: Supported
★: Wake up via ERP
☆: Wake up via System
Power On/Off
Control
(AC Resume)
◇
◇
◇
◇
◇
◇
◇
◇
Power
Management
Event
◇
Wake up
☆★
☆★
☆★
☆★
☆★
Intel DSW
Hand
Shaking
◇
◇
◇
◇
EUP/ERP
Control
◇
◇
6.8.1 Power Control
6.8.1.1 Wake Up Via Sleep State
When the system is at the normal sleep state (S3, S4, S5) or deep sleep (G3’) state, F81867 could wake
up via PWSOUT# & PME#. See below for the related registers:
Wake up by PME#
Normal Sleep State
EUP/ERP
Wake up by PWSOUT#
Normal Sleep State
EUP/ERP
◇: Supported
Index 0x2D
◇
◇
Index 0x2D
◇
CR 0A
Index 0x30
◇
◇
◇
CR0A
Index 0xE0, 0xE8
◇
CR0A
Index 0xE0, 0xE8
◇
CR0A
Index 0xF0~0xF3
◇
CR0A
Index 0xF4
◇
6.8.1.2 Wake Up Stage Detection
F81867 is counted on the chipset SLP_S3#, SLP_S4#/SLP_S5# stage, to decide the wake up stage as
below:
ACPI Stage
S0
S3
S5
SLP_S3#
H
L
L
SLP_S4# /SLP_S5#
H
H
L
96
Dec, 2011
V0.12P