F81867 Datasheet, PDF (294/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

4 PWM0_LPT_PIN_EN R/W 5VSB
3
PWM3_PIN_EN R/W 5VSB
2
PWM2_PIN_EN R/W 5VSB
1
PWM1_PIN_EN R/W 5VSB
0
PWM0_PIN_EN R/W 5VSB
0: Disable PWM0 from Pin 107.
0
1: Enable PWM0 from Pin 107.
0: Disable PWM3 from Pin 20.
0
1: Enable PWM3 from Pin 20.
0: Disable PWM2 from Pin 19.
0
1: Enable PWM2 from Pin 19.
0: Disable PWM1 from Pin 18.
0
1: Enable PWM1 from Pin 18.
0: Disable PWM0 from Pin 17.
0
1: Enable PWM0 from Pin 17.
F81867
10Hz Clock Divisor Low Byte ⎯ offset 2Ah (Available when CLK_TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
Description
The divisor of 10Hz clock. Internal 10Hz clock is used to generate WDT
7-0 CLK10HZ_DIV R/W VBAT 8’hE7 event. It is divided from 10KHz clock and could be fine tune by change its
divisor.
Multi Function Select 3 Register ⎯ offset 2Bh (Available when CLK_ TUNE_PROG_EN = 0)
Bit
Name
R/W Reset Default
Description
Pin 87 function select
7
GPIO67_EN
R/W VBAT 0 0: Pin 87 functions as S5#.
1: Pin 87 functions as GPIO67.
Pin 86 function select
6
GPIO66_EN
R/W VBAT 0 0: Pin 86 functions as DPWROK.
1: Pin 86 functions as GPIO66.
Pin 74 function select
5
GPIO65_EN
R/W VBAT 0 0: Pin 74 functions as PME#.
1: Pin 74 functions as GPIO65.
4-2
Reserved
-
-
- Reserved
Pin 102 function select
1
FANIN3_EN
R/W VBAT 1 0: Pin 102 functions as SCLT.
1: Pin 102 functions as FANIN3.
Pin 103 function select.
0
FANCTRL3_EN R/W VBAT 0 0: Pin 103 functions as GPIO70/PE.
1: Pin 103 functions as FANCTRL3.
10Hz Clock Fine Tune Count High Byte ⎯ offset 2Bh (Available when CLK_ TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
Description
7
FINE_TUNE_ST
- 5VSB
- This bit indicates the fine tune mechanism is in process.
6-4
Reserved
-
-
- Reserved
3-0 FINE_TUNE_CNT R/W 5VSB 4’h3 This is the count of 10 cycles of internal 500KHz clock with 48MHz clock.
294
Dec, 2011
V0.12P