F81867 Datasheet, PDF (307/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

12.Application Circuit
PS_ON#
PWROK
RSMRST#
VBAT
COPEN#
DPWROK
S5#
PWROK
RSMRST#
D-
D2+
D1+
VREF
VIN4
VIN3
VIN2
VIN1
R1
0
U1
VSB3V
FANIN1
FANCTL1
FANIN2
FANCTL2
SLCT
PE
BUSY
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC3V
DCD1#
RI1#
CTS1#
DTR1#
RTS1#
DSR1#
SOUT1
SIN1
DTR1#
RTS1#
SOUT1
97
98
3VSB
99
100
101
102
FANIN1
FANCTL1/PWM_DC1
FANIN2
FANCTL2/PWM_DC2
103
104
105
106
FANIN3/SLCT
GPIO70/PE/FANCTL3/PWM_DC3
GPIO71/BUSY
GPIO72/ACK#
107
108
109
110
111
112
GPIO73/SLIN#
GPIO74/INIT#/PWM0
GPIO75/ERR#/PWM1
GPIO76/AFD#/PWM2
GPIO77/STB#/PWM3
GPIO80/PD0
113
114
115
116
GPIO81/PD1
GPIO82/PD2
GPIO83/PD3
GPIO84/PD4
117
118
119
120
GPIO85/PD5
GPIO86/PD6
GPIO87/PD7
3VCC
121
122
123
124
125
DCD1#
RI1#
CTS1#
DTR1#/FAN_40_100
RTS1#/Conf ig4E_2E
126
127
128
DSR1#
SOUT1/I2C_ADDR
SIN1
GND
F81867D
F81867
DCD2#
RI2#
CTS2#
DTR2#
RTS2#
DSR2#
SOUT2
SIN2
DENSEL#/RTS6#
MOA#/SIN6
DRVA#/SOUT6
WDATA#/DCD6#
DIR#/RI6#
STEP#/CTS6#
HDSEL#/DTR6#
WGATE#/DSR6#
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
F81867
ATXPG_IN
R106 10
GPIO14
S3#
PWSOUT#
PWSIN#
ATXPG_IN
ALERT#
OVT#
PME#
5VA
PECI
BEEP
WDTRST#
GPIO14
IRRX
IRTX
LED_VCC
LED_VSB
C56
0.1U
KCLK
KDATA
64
63
62
MCLK/SDA
MDATA/SCL
I_VSB3V
GPIO07/RTS5#
61
60
59
58
GPIO06/SIN5
GPIO05/SOUT5
SLP_SUS#/GPIO04
SUS_ACK#/GPIO03
57
56
55
54
SUS_WARN#/GPIO02
ERP_CTRL1#/GPIO01
ERP_CTRL0#/GPIO00
SIN4/GPIO47
SOUT4/GPIO46
DSR4#/GPIO45
53
52
51
50
49
48
RTS4#/GPIO44
DTR4#/GPIO43
CTS4#/GPIO42
RI4#/GPIO41
47
46
45
44
DCD4#/GPIO40
SIN3/GPIO37
SOUT3/GPIO36
DSR3#/GPIO35
43
42
41
40
RTS3#/GPIO34
DTR3#/GPIO33
CTS3#/GPIO32
RI3#/GPIO31
DCD3#/GPIO30
39
38
37
36
35
GA20
KBRST#
CLKIN
34
33
C1
0.1U
KCLK
KDATA
MCLK
MDRA7TA
V3A
0_X
D1 DIODE
RTS5#
SIN5
SOUT5
SLP_SUS#
SUS_ACK#
SUS_WARN#
ERP_CTRL1#
ERP_CTRL0#
SIN4
SOUT4
DSR4#
RTS4#
DTR4#
CTS4#
RI4#
DCD4#
SIN3
SOUT3
DSR3#
RTS3#
DTR3#
CTS3#
RI3#
DCD3#
GA20
KBRST#
CLKIN
ATXPG_IN
C81 Decouple ATX
0.1U ^{power supply}
noise.
VCC5V
WPT#
R2 1K INDEX#
R3 1K TRK0#
R4 1K RDATA#
R5 1K DSKCHG#
R6 1K
J1
1
3
5
7
1
3
5
97
11
13
15
17
9
11
13
15
19
21
23
25
17
19
21
23
27
29
31
33
25
27
29
31
33
2
4
6
2
4
6
8
8 ₁₀
10
12
14
16
12
14
16
18
18
20
22
24
20
22
24
26
26
28
30
32
34
28
30
32
34
HEADER 17X2
FLOPPY
DENSEL#
INDEX#
MOA#
DRVA#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
VSB3V VCC3V
R8 R9
4.7K 4.7K
RSMRST#
PWROK
RSMRST# AND PWROK PULL UP
SOUT1
RTS1#
DTR1#
GPIO14
DTR2#
R10 R11 R12 R13 R14
560 560 560 560 560
POWER TRIP R
R10 OFF: ALARM mode
R11 OFF: ATX MODE
R12 OFF: FAN 40%
R13 OFF: CONFIG 4E
R14 OFF: 0x5C
ON: FORCE mode
ON: AT MODE
ON: FAN 100%
ON: CONFIG 2E
ON: 0x5A
DSKCHG#
WPT#
INDEX#
TRK0#
RDATA#
PCICLK
VCC3V
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#
LRESET#
DSKCHG#/DSR5#
WPT#/DTR5#
INDEX#/CTS5#
TRK0#/RI5#
RDATA#/DCD5#
307
VBAT D2 DIODEVBAT
D3 DIODEVSB3V
VCC3V VCC3V VSB3V VSB5V VBAT
C2
0.1U
C3
0.1U
C4
0.1U
C5
0.1U
C6
0.1U
(PLACE THE CAPCITOR CLOSE TO IC)
Title
Feature Integration Technology Inc.
Size Document Number
CustomF81867D
Rev
<Rev Code>
Date:
Tuesday , Nov ember 08, 2011 Sheet
1
of 8
Dec, 2011
V0.12P