F81867 Datasheet, PDF (221/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

I2C_DATA2
F81867
This is the 12^th byte of the block read protocol.
R/W 5VSB 8’h00 This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 2 High Byte – Offset E3h
Bit
Name
R/W Reset Default
Description
This is the high byte of Intel temperature interface CPU reading.
TSI_TEMP2_HI
R 5VSB
- The reading is the decimal part of CPU temperature.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 13^th byte of the block read protocol.
I2C_DATA3
R/W 5VSB 8’h00 This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 3 – Offset E4h
Bit
Name
R/W Reset Default
Description
TSI_TEMP3
R 5VSB
This is the high byte of Intel temperature interface MCH reading.
- The range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 14^th byte of the block read protocol.
I2C_DATA4
R/W 5VSB 8’h00 This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 4 – Offset E5h
Bit
Name
R/W Reset Default
Description
TSI_TEMP4
R 5VSB
This is the high byte of Intel temperature interface DIMM0
- reading. The range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 15^th byte of the block read protocol.
I2C_DATA5
R/W 5VSB 8’h00 This byte is also used as the 6th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 5 – Offset E6h
Bit
Name
R/W Reset Default
Description
This is the high byte of Intel temperature interface DIMM1
7-0
TSI_TEMP5
R 5VSB
- reading. The range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
221
Dec, 2011
V0.12P