F81867 Datasheet, PDF (56/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

PECI Master DATA10 Register ⎯ Index 4Dh
Bit
Name
R/W Reset Default
Description
7-0 PECI_DATA10 R/W 5VSB 0 For RdIAMSR(), this byte represents “DATA[47:40]”.
F81867
PECI Master DATA11 Register ⎯ Index 4Eh
Bit
Name
R/W Reset Default
Description
7-0 PECI_DATA11 R/W 5VSB 0 For RdIAMSR(), this byte represents “DATA[55:48]”.
PECI Master DATA12 Register ⎯ Index 4Fh
Bit
Name
R/W Reset Default
Description
7-0 PECI_DATA12 R/W 5VSB 0 For RdIAMSR(), this byte represents “DATA[63:56]”.
HWM Manual Control Register1 ⎯ Index 50h
Bit
Name
R/W Reset Default
Description
7
LOAD_CH
W
-
- Write 1 to load a temperature or voltage channel to be converted
6
STOP_CH
R/W 5VSB 0 Set to 1 when load a channel will generate a one-shot conversion.
5
HOLD_CH
R/W 5VSB 0 Set to 1 when load a channel will keep converting this channel.
First channel to be converted when LOAD_CH is set to 1.
00000: VCC
00001: VIN1
00010: VIN2
00011: VIN3
00100: VIN4
4:0
CHANNEL
R/W 5VSB 0 00101: VSB3V
00110: VBAT
00111: 5VSB
10000: Intel PECI
10001: T1
10010: T2
11000: AMD TSI/Intel IBEX
HWM Manual Control Status Register 1⎯ Index 51h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved
6
V_CONV_STS
R 5VSB - At least one of the voltage channels had finish converting.
5 PECI_CONV_STS WC 5VSB - PECI channel had finish converting
4 TSI_CONV_STS WC 5VSB - TSI channel had finish converting
3
Reserved
-
- Reserved
2
T2_CONV_STS
WC 5VSB - T2 channel had finish converting
1
T1_CONV_STS
WC 5VSB - T1 channel had finish converting
0
Reserved
-
- Reserved
56
Dec, 2011
V0.12P