F81867 Datasheet, PDF (289/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
0: Disable PWSIN# pin status interrupt.
1
PWSIN_INT_EN R/W 5VSB
0 1: Enable PWSIN# pin status interrupt. An interrupt will assert to μC if
PWSIN# pin status change.
0: Disable ATXPG pin status interrupt.
0 ATXPG_INT_EN R/W 5VSB 0 1: Enable ATXPG pin status interrupt. An interrupt will assert to μC if ATXPG
pin status change.
ACPI Interrupt Status Register 1 ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7 LRESET_INT_ST R/WC 5VSB 0 This bit will be set “1” if LRESET# pin status changes. Write “1” to clear.
6
S5_ST_INT_ST R/WC 5VSB 0 This bit will be set “1” if system enters S5 state. Write “1” to clear.
5
S3_ST_INT_ST R/WC 5VSB 0 This bit will be set “1” if system enters S3 state. Write “1” to clear.
4
S0_ST_INT_EN R/WC 5VSB 0 This bit will be set “1” if system enters S0 state. Write “1” to clear.
3
S5_INT_ST R/WC 5VSB 0 This bit will be set “1” if S5# pin status changes. Write “1” to clear.
2
S3_INT_ST R/WC 5VSB 0 This bit will be set “1” if S3# pin status changes. Write “1” to clear.
1
PWSIN_INT_ST R/WC 5VSB
0 This bit will be set “1” if PWSIN# pin status changes. Write “1” to clear.
0 ATXPG_INT_ST R/WC 5VSB 0 This bit will be set “1” if ATXPG pin status changes. Write “1” to clear.
ACPI Interrupt Enable Register 2⎯ Offset 12h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
1
SUS_WARN_INT_E
N
R/W
5VSB
0: Disable SUS_WARN# pin status interrupt.
0 1: Enable SUS_WARN## pin status interrupt. An interrupt will assert to μC if
SUS_WARN# pin status change.
0 SLP_SUS_INT_EN R/W 5VSB
0: Disable SLP_SUS# pin status interrupt.
0 1: Enable SLP_SUS# pin status interrupt. An interrupt will assert to μC if
SLP_SUS# pin status change.
ACPI Interrupt Status Register 2 ⎯ Offset 13h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
1 SUS_WARN_INT_ST R/WC 5VSB 0 ^{This bit will be set “1” if SUS_WARN# pin status changes. Write “1” to clear.}
0 SLP_SUS_INT_ST R/WC 5VSB 0 ^{This bit will be set “1” if SLP_SUS# pin status changes. Write “1” to clear.}
7.20.13 Configuration Register (Base Address 0x2400, 256 bytes)
Chip ID 1 Register ⎯ offset 20h (Powered by I_VSB3V)
Bit
Name
R/W Reset Default
7-0
CHIP_ID1
R
-
0x10 Chip ID 1.
Chip ID 2 Register ⎯ offset 21h (Powered by I_VSB3V)
Bit
Name
R/W Reset Default
Description
Description
289
Dec, 2011
V0.12P