F81867 Datasheet, PDF (13/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
¾ All GPIO supports digit IO for Input/Output control, Output data control, input status.
¾ Support High/Low Level/Pulse, Open Drain/Push Pull function selection
¾ All GPIO could be accessed via 3 ways: configuration register port (4E/2E), index/data
port and directly access to GPIO only (digital I/O). Please refer to the related register for
detail.
Watch Dog Timer
¾ Time resolution minute/second by option
¾ Maximum 256 minutes or 256 seconds
¾ Output signal via WDTRST#/PWROK
¾ WDT could also wake up via PME#, PSWOUT#
Power Saving Function
¾ G3-like Timing Control
¾ Comply With ERP Lot 6.0
¾ Built in Soft Start Function for Two Control Pins with VSB Power Sources Control.
¾ Event In via GPIO0x, GPIO1x, RI1#, and RI2#
Support Intel Cougar Point Timing (DSW)
UART
¾ Provide 6 fully functional UART
¾ 6 high-speed 16C550/16C650/16C750/16C850 compatible UARTs
¾ Provide auto flow control function
¾ Baud rate supports 115.2K, max. up to 1.5M
¾ Support IRQ 3,4,5,6,7,8,9,10,11 sharing
¾ Provide Multi drop (9-bits) Function for Gaming Machine
¾ Support IrDA version 1.0 SIR protocol (Multi with UART 6)
¾ Support Ring-In Wake Up via RI1# and RI2#
Infrared
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
(Multi with UART 6)
Provide ATX Emulates AT Function
Provide Serial ID Function
¾ Provide 16 bytes for fixed Fintek serial ID
13
Dec, 2011
V0.12P