F81867 Datasheet, PDF (91/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
*GPIO2 Data Port ⎯ Offset 08h
Bit
Name
R/W Reset Default
Description
GPIO2 Data Control, this byte is available when GPIODEC_RANGE is set.
Write data to this byte will change the value of GPIO20_VAL ~ GPIO27_VAL
7-0
GPIO2_DATA R/W 5VSB
- in configuration register as writing data to index 0xD1.
Read data from this byte will read the pin status of GPIO20_IN ~ GPIO27_IN
as the value in index 0xD2
*GPIO3 Data Port ⎯ Offset 09h
Bit
Name
R/W Reset Default
Description
GPIO3 Data Control, this byte is available when GPIODEC_RANGE is set.
Write data to this byte will change the value of GPIO30_VAL ~ GPIO37_VAL
7-0
GPIO3_DATA R/W LRESET# - in configuration register as writing data to index 0xC1.
Read data from this byte will read the pin status of GPIO30_IN ~ GPIO37_IN
as the value in index 0xC2
GPIO4 Data Port ⎯ Offset 0Ah
Bit
Name
R/W Reset Default
Description
GPIO4 Data Control, this byte is available when GPIODEC_RANGE is set.
Write data to this byte will change the value of GPIO40_VAL ~ GPIO47_VAL
7-0
GPIO4_DATA R/W LRESET# - in configuration register as writing data to index 0xB1.
Read data from this byte will read the pin status of GPIO40_IN ~ GPIO47_IN
as the value in index 0xB2
6.6.2 GPIOx status
Z means high impendence.
If the external circuit is pull high then the pin status is "H"; else if the external circuit is pull low then the pin
status is "L".
User define means by programming the configure register.
GPIO0x
Pin
Name
52
GPIO00
53
GPIO01
54
GPIO02
55
GPIO03
56
GPIO04
57
GPIO05
58
GPIO06
59
GPIO07
G3 -> S5
L
L
Z
L
Z
Z
Z
Z
PIN STATUS
S0
S3
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
user define
S5
user define
user define
user define
user define
user define
user define
user define
user define
Register
Power
Well
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
Register
Reset Signal
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
Pin
Power
Well
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
91
Dec, 2011
V0.12P