F81867 Datasheet, PDF (235/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
4-1
Reserved
-
-
0 Reserved
0
V0_VP_EN R/W VBAT*
0 Voltage-Protect shut down enable for 3VCC
Voltage-Protect Status Register (Powered by VBAT) ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7-6
Reserved
-
-
0 Reserved.
This bit is voltage-protect status. Once one of the monitored
voltages (3VCC, VIN5, VIN6) over its related over-voltage limits
R/W VBAT/
0
V_EXC_VP
0 or under its related under-voltage limits and if the related
C 5VSB*
voltage-protect shut down enable bit is set, this bit will be set to 1.
Write a 1 to this bit will clear it to 0. (This bit is powered by VBAT)
*Reset by VBAT when OVP_MODE is “0”, Reset by 5VSB when OVP_MODE is “1”
Voltage-Protect Configuration Register ⎯ Offset 12h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
PSON# de-active time select for voltage protection.
00: PSON# tri-state 0.5 sec and then inverted of S3# when over
voltage or under voltage occurs.
01: PSON# tri-state 1 sec and then inverted of S3# when over
3-2
PU_TIME R/W VBAT 2’h1 voltage or under voltage occurs.
10: PSON# tri-state 2 sec and then inverted of S3# when over
voltage or under voltage occurs.
11: PSON# tri-state 4 sec and then inverted of S3# when over
voltage or under voltage occurs.
VP_EN_DELAY could set the delay time to start voltage
protecting after VDD power is ok when OVP_MODE is 1.
(OVP_MODE is strapped by RTS1# pin)
1-0 VP_EN_DELAY R/W VBAT 2’h2 00: bypass
01: 50ms
10: 100ms
11: 200ms
Voltage1 PME# Enable Register ⎯ Offset 14h
Bit
Name
R/W Reset Default
7-2
Reserved
-
-
0 ^Reserved
Description
235
Dec, 2011
V0.12P