F81867 Datasheet, PDF (169/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
0: No SMI event.
1 GPIO81_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO81 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
0: No SMI event.
0 GPIO80_SMI_ST R/W LRESET# 0 1: A SMI event will set if GPIO80 input is changed.
This bit is available in input mode. Write “1” to this bit will clear the status.
7.8 GPIO8x Scan Code Registers
Register
0x[HEX]
D8
Register Name
GPIO8 Make Code 0 Register
D9
GPIO8 Make Code 1 Register
DA
GPIO8 Make Code 2 Register
DB
GPIO8 Make Code 3 Register
DC
GPIO8 Make Code 4 Register
DD
GPIO8 Make Code 5 Register
DE
GPIO8 Make Code 6 Register
DF
GPIO8 Make Code 7 Register
C8
GPIO8 Pre Code 0 Register
C9
GPIO8 Pre Code 1 Register
CA
GPIO8 Pre Code 2 Register
CB
GPIO8 Pre Code 3 Register
CC
GPIO8 Pre Code 4 Register
CD
GPIO8 Pre Code 5 Register
CE
GPIO8 Pre Code 6 Register
CF
GPIO8 Pre Code 7 Register
B8
GPIO8 Scan Code 0 Control Register
B9
GPIO8 Scan Code 1 Control Register
BA
GPIO8 Scan Code 2 Control Register
BB
GPIO8 Scan Code 3 Control Register
BC
GPIO8 Scan Code 4 Control Register
BD
GPIO8 Scan Code 5 Control Register
BE
GPIO8 Scan Code 6 Control Register
BF
GPIO8 Scan Code 7 Control Register
AC-AD Reserved for Fintek.
AE
GPIO8 Function Select 1 Register
AF
GPIO8 Function Select 2 Register
MSB
00
00
00
00
00
00
00
00
11
11
11
11
11
11
11
11
00
00
00
00
00
00
00
00
00
00
00
Default Value
0000
0000
0000
0000
0000
0000
0000
0000
1000
1000
1000
1000
1000
1000
1000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
LSB
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
169
Dec, 2011
V0.12P