F81867 Datasheet, PDF (298/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
7.20.15 CIR μC Side Register (Base Address 0x2600, 256 bytes)
CIR – CIR FIFO Register – Index 2300h
Bit
Name
R/W Reset Default
Description
7-0
CIR_FIFO
Receiver Buffer is read only register. When the CIR pulse train has been
R 5VSB 00h detected and passed by the internal signal filter, the data sampled and
shifted into shifter register will be written into Receiver Buffer Register
CIR – Interrupt Enable Register – Index 2301h
Bit
Name
R/W Reset Default
Description
7
Interrupt_EN
R/W 5VSB 0b Write 1 to enable CIR interrupt.
6-0 Reserved
-
-
00h Reserved
CIR – Interrupt Status Register – Index 2302h
Bit
Name
R/W Reset Default
Description
7-4
FIFO_CNT
R 5VSB 0h This nibble indicates the number of byte that RX data receive.
3
FIFO_RST
R/W 5VSB 0b Write 1 to reset CIR FIFO.
2
Reserved
-
-
0b Reserved
1
Data_Lost
R 5VSB 0b This bit indicates FIFO data lost, and write 1 to clear this bit.
0
Ready
R 5VSB 0b This bit indicates RX data ready, and write 1 to clear this bit.
CIR – Baud Rate Low Byte Register – Index 2303h
Bit
Name
R/W Reset Default
Description
7-0
Baud_Lo
R/W 5VSB A5h The registers of BLL are baud rate divisor latch.
CIR – Baud Rate High Byte Register – Index 2304h
Bit
Name
R/W Reset Default
Description
7-0
Baud_Hi
R/W 5VSB 01h The registers of BHL are baud rate divisor latch.
CIR – Waveform Logic 1 Data Register – Index 2305h
Bit
Name
R/W Reset Default
Description
7-0
WaveH
R/W 5VSB 80h The registers of WaveH indicate RX logic 1 waveform
CIR – Waveform Logic 0 Data Register – Index 2306h
Bit
Name
R/W Reset Default
Description
7-0
WaveL
R/W 5VSB 80h The registers of WaveL indicate RX logic 0 count number
CIR – Waveform Logic 1 Count Register – Index 2307h
Bit
Name
R/W Reset Default
Description
7-0 WaveH_Count R/W 5VSB 04h The registers of WaveH_Count indicate RX logic 1 count number
298
Dec, 2011
V0.12P