F81867 Datasheet, PDF (218/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

Configuration Register 2⎯ Offset 04h
Bit
Name
7
Reserved
R/W Reset Default
-
-
- ^Reserved
Description
6
BIAS_EN
R/W 5VSB
0 Reserved for Fintek use only
5-1
Reserved
R/W
-
- ^Reserved
0
S3_HM_EN R/W 5VSB
0 Set 1 to enable monitoring at S3 state.
TSI Control Register1 ⎯ Offset 08h
Bit
Name
R/W Reset Default
Description
7-1
TSI_ADDR
R/W 5VSB
26h ^{AMD TSI or Intel IBex slave address}
0
Reserved
-
-
- ^Reserved
F81867
TSI Control Register2 ⎯ Offset 09h
Bit
Name
R/W Reset Default
Description
7-1 SMB_ADDR R/W 5VSB
0 ^{Address for I2C master to use a block write command}
0
Reserved
-
-
- ^Reserved
Configuration Register 3 ⎯ Offset 0Ah
Bit
Name
R/W Reset Default
Description
7
BETA_EN2 R/W 5VSB
0
0: disable the T2 beta compensation.
1: enable the T2 beta compensation.
6
BETA_EN1 R/W 5VSB
0
0: disable the T1 beta compensation.
1: enable the T1 beta compensation.
5
INTEL_SEL R/W 5VSB
This bit is used to select AMD TSI or Intel IBEX when TSI_EN is
1
set to 1.
0: Select AMD
1: Select Intel
4 MXM_MODE R/W LRESET# 0 Reserved.
PECI (VTT) voltage selection.
00: VTT is 1.23V
3-2
VTT_SEL
R/W 5VSB
0 01: VTT is 1.13V
10: VTT is 1.00V
11: VTT is 1.00V
1
TSI_EN
R/W 5VSB
0 ^{Set this bit 1 to enable AMD TSI or Intel IBEX function}
0
PECI_EN
R/W LRESET#
0 ^{Set this bit 1 to enable Intel PECI function}
218
Dec, 2011
V0.12P