F81867 Datasheet, PDF (260/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
7.20.9 GPIO μC Side Register (Base Address 0x2100, 256 bytes)
GPIO0 Output Enable Register ⎯ offset F0h.
Bit
Name
R/W Reset Default
Description
0: GPIO07 is in input mode.
7
GPIO07_OE
R/W 5VSB 0
1: GPIO07 is in output mode.
0: GPIO06 is in input mode.
6
GPIO06_OE
R/W 5VSB 0
1: GPIO06 is in output mode.
0: GPIO05 is in input mode.
5
GPIO05_OE
R/W 5VSB 0
1: GPIO05 is in output mode.
0: GPIO04 is in input mode.
4
GPIO04_OE
R/W 5VSB 0
1: GPIO04 is in output mode.
0: GPIO03 is in input mode.
3
GPIO03_OE
R/W 5VSB 0
1: GPIO03 is in output mode.
0: GPIO02 is in input mode.
2
GPIO02_OE
R/W 5VSB 0
1: GPIO02 is in output mode.
0: GPIO01 is in input mode.
1
GPIO01_OE
R/W 5VSB 0
1: GPIO01 is in output mode.
0: GPIO00 is in input mode.
0
GPIO00_OE
R/W 5VSB 0
1: GPIO00 is in output mode.
GPIO0 Output Data Register ⎯ offset F1h
Bit
Name
R/W Reset Default
Description
GPIO07 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO07. Auto clear when pulse is finished.
7
GPIO07_VAL R/W 5VSB 0 When level mode is selected, write 0/1 to this bit will set the level of GPIO07.
0: outputs 0 when in output mode.
1: outputs1 when in output mode. GPIO07 will be tri-state if GPIO07_DRV is
clear to “0”.
GPIO06 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO06. Auto clear when pulse is finished.
6
GPIO06_VAL R/W 5VSB 0 When level mode is selected, write 0/1 to this bit will set the level of GPIO06.
0: outputs 0 when in output mode.
1: outputs1 when in output mode. GPIO06 will be tri-state if GPIO06_DRV is
clear to “0”.
GPIO05 supports pulse mode.
When pulse mode is selected, write “1” to this bit will assert a pulse from
GPIO05. Auto clear when pulse is finished.
5
GPIO05_VAL R/W 5VSB 0 When level mode is selected, write 0/1 to this bit will set the level of GPIO05.
0: outputs 0 when in output mode.
1: outputs1 when in output mode. GPIO05 will be tri-state if GPIO05_DRV is
clear to “0”.
260
Dec, 2011
V0.12P