F81867 Datasheet, PDF (110/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

PWROK Signals
F81867
VDD3VOK
ATXPWGD
DELAY
PWROK
Fig 6-24
PWROK is delayed 400ms (default) as VCC arrives 2.8V, and the delay timing can be programmed via
register (100ms ~ 400ms).
6.9 UART
The F81867 provides up to 6 UART ports and supports IRQ sharing for system application. They are
compatible with 16C550/16C650/16C750 and 16C850 .The UARTs are used to convert data between parallel
format and serial format. They convert parallel data into serial format on transmission and serial format into
parallel data on receiver side. The serial format is formed by one start bit, followed by five to eight data bits, a
parity bit if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control capability
and an interrupt system that may be software trailed to the computing time required to handle the communication
link. They have FIFO mode to reduce the number of interrupts presented to the host. Both receiver and
transmitter have a 128-byte FIFO.
The UART control register control & define the asynchronous protocol data communications including data
length, stop bit, parity & baud rate selection.
The below content is about the UARTs device register descriptions. All the registers are for software porting
reference.
Receiver Buffer Register ⎯ Base + 0
Bit
Name
R/W Reset Default
Description
7-0
RBR
The data received.
R LRESET# 00h _{Read only when LCR [7] is 0}
Transmitter Holding Register ⎯ Base + 0
Bit
Name
R/W Reset Default
Description
7-0
THR
Data to be transmitted.
W LRESET# 00h _{Write only when LCR [7] is 0}
Divisor Latch (LSB) ⎯ Base + 0
Bit
Name
R/W Reset Default
Description
Baud generator divisor low byte.
7-0
DLL
R/W LRESET# 01h _{Access only when LCR [7] is 1.}
110
Dec, 2011
V0.12P