F81867 Datasheet, PDF (208/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
7.20.1Interrupt Control μC Side Register (Base Address 0x1000, 256 bytes)
Interrupt Status Register ⎯ Offset 01h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved.
0: No CIR interrupt event.
6
CIR_INT_ST R/WC 5VSB 0
1: A CIR interrupt event occurs. Write “1” to clear this bit.
0: No 0x80 port interrupt event.
5
P80_INT_ST R/WC 5VSB 0
1: A 0x80 port interrupt event occurs. Write “1” to clear this bit.
0: No H2E interrupt event.
4
H2E_INT_ST R/WC 5VSB 0
1: A H2E interrupt event occurs. Write “1” to clear this bit.
0: No ACPI interrupt event.
3
ACPI_INT_ST R/WC 5VSB 0
1: An ACPI interrupt event occurs. Write “1” to clear this bit.
0: No KBC interrupt event.
2
KBC_INT_ST R/WC 5VSB 0
1: A KBC interrupt event occurs. Write “1” to clear this bit.
0: No GPIO interrupt event.
1
GPIO_INT_ST R/WC 5VSB 0
1: A GPIO interrupt event occurs. Write “1” to clear this bit.
0: No hardware monitor interrupt event.
0
HM_INT_ST R/WC 5VSB 0
1: A hardware monitor interrupt event occurs. Write “1” to clear this bit.
Interrupt Enable Register ⎯ Offset 03h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved.
0: Disable CIR interrupt.
6
CIR_INT_EN R/WC 5VSB 0
1: Enable CIR interrupt.
0: Disable 0x80 Port interrupt.
5
P80_INT_EN R/WC 5VSB 0
1: Enable 0x80 Port interrupt.
0: Disable Host to EC interrupt.
4
H2E_INT_EN R/WC 5VSB 0
1: Enable Host to EC interrupt.
0: Disable ACPI interrupt.
3
ACPI_INT_EN R/WC 5VSB 0
1: Enable ACPI interrupt.
0: Disable KBC interrupt.
2
KBC_INT_EN R/WC 5VSB 0
1: Enable KBC interrupt.
0: Disable GPIO interrupt.
1
GPIO_INT_EN R/WC 5VSB 0
1: Enable GPIO interrupt.
0: Disable HM interrupt.
0
HM_INT_EN R/WC 5VSB 0 1: Enable HM interrupt.
The peripheral interrupt is asserted to INT1# of μC.
Interrupt Polarity Register ⎯ Offset 05h
Bit
Name
R/W Reset Default
Description
7
Reserved
-
-
- Reserved.
0: Rising edge of event will trigger an interrupt.
6
CIR_INT_POL R/WC 5VSB 0
1: Falling edge of event will trigger an interrupt.
208
Dec, 2011
V0.12P