F81867 Datasheet, PDF (231/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

5-4 OVT_TEMP_SEL R/W 5VSB
3-2
Reserved
R/W -
1-0 HIGH_ TEMP_SEL R/W 5VSB
F81867
Select the source temperature for T1 OVT Limit.
0: Select T1 to be compared to Temperature 1 OVT Limit.
1: Select CPU temperature from PECI to be compared to
Temperature 1 OVT Limit.
0
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 OVT Limit.
3: Select the MAX temperature from Intel PCH I2C to be
compared to Temperature 1 OVT Limit.
0 Reserved
Select the source temperature for T1 High Limit.
0: Select T1 to be compared to Temperature 1 High Limit.
1: Select CPU temperature from PECI to be compared to
Temperature 1 High Limit.
0
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 High Limit.
3: Select the MAX temperature from Intel PCH I2C to be
compared to Temperature 1 High Limit.
OVT and Alert Output Enable Register 1 ⎯ Offset 66h
Bit
Name
R/W Reset Default
7
Reserved
R/W -
0 Reserved
Description
6 EN_T2_ALERT R/W 5VSB
Enable temperature 2 alert event (asserted when temperature
0
over high limit)
5 EN_T1_ALERT R/W 5VSB
4 EN_T0_ALERT R/W 5VSB
3
Reserved
-
-
Enable temperature 1 alert event (asserted when temperature
0
over high limit)
0
Enable temperature 0 alert event (asserted when temperature
over high limit)
0 Reserved
2
EN_T2_OVT R/W 5VSB 0 Enable over temperature (OVT) mechanism of temperature2.
1
EN_T1_OVT R/W 5VSB 1 Enable over temperature (OVT) mechanism of temperature1.
0
EN_T0_OVT R/W 5VSB 0 ^{Enable over temperature (OVT) mechanism of temperature0.}
Reserved ⎯Offset 67~69h
Bit
Name
R/W Reset Default
7-0
Reserved
-
-
- Reserved
Description
231
Dec, 2011
V0.12P