F81867 Datasheet, PDF (209/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

0: Rising edge of event will trigger an interrupt.
5
P80_INT_POL R/WC 5VSB 0
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
4
H2E_INT_POL R/WC 5VSB 0
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
3
ACPI_INT_POL R/WC 5VSB 0
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
2
KBC_INT_POL R/WC 5VSB 0
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
1
GPIO_INT_POL R/WC 5VSB
0
1: Falling edge of event will trigger an interrupt.
0: Rising edge of event will trigger an interrupt.
0
HM_INT_POL R/WC 5VSB 0
1: Falling edge of event will trigger an interrupt.
F81867
Interrupt Status 3 Register ⎯ Offset 10h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
0: No power down event
1
PD_INT_ST R/WC 5VSB 0 1: A power down event occurs. It is set by falling edge of PWROK. It is
cleared by read this bit.
0 DBPORT_INT_ST R/WC 5VSB
0: No debug port event.
0
1: A debug port interrupt event occurs. Clear by reading this bit.
Power Fail Register ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
1
PWROK
R 5VSB 0 Status of PWROK.
0
PD_INT_EN R/WC 5VSB 0 Set “1” to enable power fail interrupt.
7.20.2 General Control μC Side Register (Base Address 0x1100, 256 bytes)
Chip ID 1 Register ⎯ Offset 00h
Bit
Name
R/W Reset Default
7-0
CHIPID1
R
-
0x00 Chip ID 1
Description
Chip ID 2 Register ⎯ Offset 01h
Bit
Name
R/W Reset Default
7-0
CHIPID2
R
-
0x95 Chip ID 2
Description
μC Reset Select Register ⎯ Offset 04h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved.
Description
209
Dec, 2011
V0.12P