F81867 Datasheet, PDF (258/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
FAN3 SEGMENT 2 SPEED COUNT – Offset CBh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN3_MODE(CR96)
7-0 SEC2SPEED3 R/W 5VSB ^{D9h 2’b00: The value that set in this byte is the relative expect fan}
(85%) _{speed % of the full speed in this temperature section.}
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN3 SEGMENT 3 SPEED COUNT – Offset CCh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
B2h ^{FAN3_MODE(CR96)}
7-0
SEC3SPEED3
R/W
5VSB
(70%)
2’b00: The value that set in this byte is the relative expect fan
speed % of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN3 SEGMENT 4 SPEED COUNT – Offset CDh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN3_MODE(CR96)
7-0
SEC4SPEED3
R/W
5VSB
99h 2’b00: The value that set in this byte is the relative expect fan
(60%) speed % of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN3 SEGMENT 5 SPEED COUNT – Offset CEh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN3_MODE(CR96)
7-0
SEC5SPEED3
R/W
5VSB
80h 2’b00: The value that set in this byte is the relative expect fan
(50%) speed % of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN3 Temperature Mapping Select – Offset CFh
Bit
Name
R/W Reset Default
Description
FAN3_TEMP_
This bit companies with FAN3_TEMP_SEL select the
7
R/W 5VSB 0
SEL_DIG
temperature source for controlling FAN3.
258
Dec, 2011
V0.12P