F81867 Datasheet, PDF (295/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
10Hz Clock Fine Tune Count Low Byte ⎯ offset 2Ch (Available when CLK_ TUNE_PROG_EN = 1
Bit
Name
R/W Reset Default
Description
7-0 FINE_TUNE_CNT R/W 5VSB 4’h3 This is the count of 10 cycles of internal 500KHz clock with 48MHz clock.
GPIO0 Enable Register ⎯ offset 2Ch (Available when CLK_PROG_EN = 0 and GPIO_PROG_SEL = 2’b00)
Bit
Name
R/W Reset Default
Description
7-5
Reserved
-
-
- Reserved
Pin 56 function select.
4
GPIO04_EN
R/W VBAT 0 0: Pin 56 functions as SLP_SUS#.
1: Pin 56 functions as GPIO04.
Pin 55 function select.
3
GPIO03_EN
R/W VBAT 0 0: Pin 55 functions as SUS_ACK#.
1: Pin 55 functions as GPIO03.
Pin 54 function select.
2
GPIO02_EN
R/W VBAT 0 0: Pin 54 functions as SUS_WARN#.
1: Pin 54 functions as GPIO02.
Pin 53 function select.
1
GPIO01_EN
R/W VBAT 0 0: Pin 53 functions as ERP_CTRL1#.
1: Pin 53 functions as GPIO01.
Pin 52 function select.
0
GPIO00_EN
R/W VBAT 0 0: Pin 52 functions as ERP_CTRL0#.
1: Pin 52 functions as GPIO00.
GPIO1 Enable Register ⎯ offset 2Ch (Available when CLK_PROG_EN = 0 and GPIO_PROG_SEL = 2’b01)
Bit
Name
R/W Reset Default
Description
Pin 72 function select.
7
GPIO17_EN
R/W VBAT 0 0: Pin 72 functions as PECI.
1: Pin 72 functions as GPIO17.
Pin 71 function select.
6
GPIO16_EN
R/W VBAT 0 0: Pin 71 functions as BEEP.
1: Pin 71 functions as GPIO16.
Pin 70 function select.
5
GPIO15_EN
R/W VBAT 0 0: Pin 70 functions as WDTRST#.
1: Pin 70 functions as GPIO15.
4
Reserved
-
-
- Reserved
Pin 68 function select.
0: Pin 68 functions as IRRX.
3
GPIO13_EN
R/W VBAT 1
1: Pin 68 functions as GPIO13.
If SDA_PIN68_EN is set, pin 68 will function as SDA.
295
Dec, 2011
V0.12P