F81867 Datasheet, PDF (63/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

1-0 IIR-QUEUR_DIG
F81867
The queue time for second filter to quickly update values. (for CPU
temperature from PECI or TSI interface)
00: 8 timers.
R/W 5VSB 2’b10
01: 12 times.
10: 16 times. (default)
11: 24 times.
6.4.2.4 Voltage Setting
Voltage-Protect Shut Down Enable Register ⎯ Index 10h
Bit
Name
R/W Reset Default
7
Reserved
-
-
0 Reserved.
Description
6
V3_VP_EN
R/W VBAT* 0 Voltage-Protect shut down enable for VIN3
5
V2_VP_EN
R/W VBAT* 0 Voltage-Protect enable for VIN2
4-1
Reserved
-
-
0 Reserved
0
VCC_VP_EN R/W VBAT* 0 Voltage-Protect shut down enable for 3VCC
Voltage-Protect Status Register ⎯ Index 11h
Bit
Name
R/W Reset Default
Description
7-6
Reserved
-
-
0 Reserved.
This bit is voltage-protect status. Once one of the monitored voltages
(3VCC, VIN2, VIN3) over its related over-voltage limits or under its related
VBAT/
0
V_EXC_VP
R/WC
0 under-voltage limits and if the related voltage-protect shut down enable bit
5VSB*
is set, this bit will be set to 1. Write a 1 to this bit will clear it to 0. (This bit is
powered by VBAT)
*Reset by VBAT when OVP_MODE is “0”, Reset by 5VSB when OVP_MODE is “1”
Voltage-Protect Configuration Register ⎯ Index 12h
Bit
Name
R/W Reset Default
7-4
Reserved
-
-
- Reserved.
Description
63
Dec, 2011
V0.12P