F81867 Datasheet, PDF (293/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

5-4 UR3_FUNC_SEL R/W 5VSB
3 SCL3_PIN76_EN R/W 5VSB
2 SDA3_PIN71_EN R/W 5VSB
1 SDA2_PIN68_EN R/W 5VSB
0 SCL2_PIN67_EN R/W 5VSB
F81867
UART3 Function Select.
00: No UART3 pin. Pin 36 ~ 43 are all GPIOs.
01: Simple UART: only SIN3 & SOUT3 are available. Pin 42 will be function
0 as SOUT3 and Pin 43 will be function as SIN3.
10: Simple UART with RTS#. In addition to simple UART, pin 40 will be
function as RTS3#.
11: Full UART: pin 36 ~ 43 will be function as UART pins.
0: Disable SCL from pin 76.
1: Enable SCL from pin 76.
0 _{There is only one slave in the current design, it is recommended to select}
only one pin for SCL. When multi pins are selected, the priority of these bits
is MO_I2C_EN > SCL_PIN76_EN > SCL_PIN67_EN.
0: Disable SDA from pin 76.
1: Enable SDA from pin 76.
0 _{There is only one slave in the current design, it is recommended to select}
only one pin for SDA. When multi pins are selected, the priority of these bits
is MO_I2C_EN > SDA_PIN71_EN > SDA_PIN68_EN.
0: Disable SDA from pin 68.
1: Enable SDA from pin 68.
1 _{There is only one slave in current design, it is recommended to select only}
one pin for SDA. When multi pins are selected, the priority of these bits is
MO_I2C_EN > SDA_PIN71_EN > SDA_PIN68_EN.
0: Disable SCL from pin 67.
1: Enable SCL from pin 67.
1 _{There is only one slave in current design, it is recommended to select only}
one pin for SCL. When multi pins are selected, the priority of these bits is
MO_I2C_EN > SCL_PIN76_EN > SCL_PIN67_EN.
10Hz Clock Divisor High Byte ⎯ offset 29h (Available when CLK_ TUNE_PROG_EN = 1)
Bit
Name
R/W Reset Default
Description
7 FINE_TUNE_START W
-
Write “1” to start fine tune mechanism. The hardware will start to count 10
- cycle internal 500KHz clock with 48MHz clock. The count will present in
index 0x2A, 0x2B.
6-4
Reserved
-
-
- Reserved
The divisor of 10Hz clock. Internal 10Hz clock is used to generate WDT
3-0 CLK10HZ_DIV R/W VBAT 4’h3 event. It is divided from 10KHz clock and could be fine tune by change its
divisor.
Multi Function Select 2 Register ⎯ offset 2Ah (Available when CLK_ TUNE_PROG_EN = 0)
Bit
Name
R/W Reset Default
Description
7 PWM3_LPT_PIN_EN R/W 5VSB
0: Disable PWM3 from Pin 110.
0
1: Enable PWM3 from Pin 110.
6 PWM2_LPT_PIN_EN R/W 5VSB
0: Disable PWM2 from Pin 109.
0
1: Enable PWM2 from Pin 109.
5 PWM1_LPT_PIN_EN R/W 5VSB
0: Disable PWM1 from Pin 108.
0
1: Enable PWM1 from Pin 108.
293
Dec, 2011
V0.12P