F81867 Datasheet, PDF (204/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7.19 UART6 Registers (CR15)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
Device Enable Register
60
Base Address High Register
61
Base Address Low Register
70
IRQ Channel Select Register
F0
IRQ Share Register
F1
IR Mode Register
F2
Clock Select Register
F4
9bit-mode Slave Address Register
F5
9bit-mode Slave Address Mask Register
F0
IRQ Share Register
F6
FIFO Mode Register
F81867
MSB
--
00
00
--
00
--
--
--
00
00
00
Default Value
----
0000
0000
- - 00
0000
- 001
- 000
----
0000
0000
000 -
LSB
-0
00
00
11
00
00
00
00
00
00
00
UART 6 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
- Reserved
0: disable UART 6 I/O Port.
0
UART6_EN
R/W LRESET# 0
1: enable UART 6 I/O Port.
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 00h The MSB of UART 6 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# 00h The LSB of UART 6 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0 SELUART6IRQ R/W LRESET# 3h Select the IRQ channel for UART 6.
IRQ Share Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: normal UART function
7
9BIT_MODE
R/W LRESET# 0 ^{1: enable 9-bit mode (multi-drop mode).}
In the 9-bit mode, the parity bit becomes the address/data bit.
204
Dec, 2011
V0.12P