F81867 Datasheet, PDF (249/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
FAN1 SEGMENT 2 SPEED COUNT – Offset ABh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN1_MODE(CR96)
7-0 SEC2SPEED1 R/W 5VSB ^{D9h 2’b00: The value that set in this byte is the relative expect fan}
(85%) _{speed % of the full speed in this temperature section.}
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN1 SEGMENT 3 SPEED COUNT Register – Offset ACh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN1_MODE(CR96)
B2h ^{2’b00: The value that set in this byte is the relative expect fan}
7-0 SEC3SPEED1 R/W 5VSB _{(70%) speed % of the full speed in this temperature section.}
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN1 SEGMENT 4 SPEED COUNT Register – Offset ADh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN1_MODE(CR96)
7-0
SEC4SPEED1
R/W
5VSB
99h ^{2’b00: The value that set in this byte is the relative expect fan}
(60%) _{speed % of the full speed in this temperature section.}
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
FAN1 SEGMENT 5 SPEED COUNT Register – Offset AEh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the
FAN1_MODE(CR96)
80h _{2’b00: The value that set in this byte is the relative expect fan}
7-0 SEC5PEED1 R/W 5VSB (50%)
speed % of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
249
Dec, 2011
V0.12P