F81867 Datasheet, PDF (195/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7.16 UART3 Registers (CR12)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
Device Enable Register
60
Base Address High Register
61
Base Address Low Register
F0
IRQ Share Register
F2
Clock Select Register
F4
9bit-mode Slave Address Register
F5
9bit-mode Slave Address Mask Register
F0
IRQ Share Register
F6
FIFO Mode Register
F81867
MSB
--
00
11
--
00
--
00
00
00
Default Value
----
0000
1010
- - 00
00- -
----
0000
0000
000 -
LSB
-1
11
00
11
00
00
00
00
00
UART 3 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
- Reserved
0: disable UART 3 I/O Port.
0
UART3_EN
R/W LRESET# 1
1: enable UART 3 I/O Port.
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 03h The MSB of UART 3 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# E8h The LSB of UART 3 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0 SELUART3IRQ R/W LRESET# 3h Select the IRQ channel for UART 3.
IRQ Share Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: normal UART function
7
9BIT_MODE
R/W LRESET# 0 ^{1: enable 9-bit mode (multi-drop mode).}
In the 9-bit mode, the parity bit becomes the address/data bit.
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
6
AUTO_ADDR
R/W LRESET# 0 _{1: the SM2 bit will be cleared by hardware according to the sent address and}
the given address (or broadcast address derived by SADDR and SADEN)
195
Dec, 2011
V0.12P