F81867 Datasheet, PDF (222/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

I2C_DATA6
F81867
This is the 16^th byte of the block read protocol.
R/W 5VSB 8’h00 This byte is also used as the 7th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 6 – Offset E7h
Bit
Name
R/W Reset Default
Description
TSI_TEMP6
R 5VSB
This is the high byte of Intel temperature interface DIMM2
- reading. The range is 0~255^ºC.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 17^th byte of the block read protocol.
I2C_DATA7
R/W 5VSB 8’h00 This byte is also used as the 8th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
TSI Temperature 7 – Offset E8h
Bit
Name
R/W Reset Default
Description
TSI_TEMP7
R 5VSB
This is the high byte of Intel temperature interface DIMM3
reading. The range is 0~255^ºC. The above 9 bytes could also be
-
used as the read data of block read protocol if the TSI is disable
7-0
or pending.
This is the 18^th byte of the block read protocol.
I2C_DATA8
R/W 5VSB 8’h00 This byte is also used as the 9th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
I2C Data Buffer 9 – Offset E9h
Bit
Name
R/W Reset Default
Description
This is the 18^th byte of the block read protocol.
7-0
I2C_DATA9
R/W 5VSB FFh This byte is also used as the 9th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
Block Write Count Register – Offset ECh
Bit
Name
R/W Reset Default
Description
This bit is used to select the register in Offset E0h to E9h.
7 MCH_BANK_SEL R/W 5VSB 0 Set “0” to read the temperature bank and “1” to access the data
bank.
6
Reserved
-
-
0 Reserved
5-0 BLOCK_WR_CNT R/W 5VSB
Use the register to specify the byte count of block write protocol.
0
Support up to 10 bytes.
222
Dec, 2011
V0.12P