F81867 Datasheet, PDF (112/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
Line Control Register (LCR) ⎯ Base + 3
Bit
Name
R/W Reset Default
Description
0: Divisor Latch can’t be accessed.
7
DLAB
R/W LRESET# 0 _{1: Divisor Latch can be accessed via Base and Base+1.}
6
SETBRK
R/W LRESET#
0
0: Transmitter is in normal condition.
1: Transmit a break condition.
5
STKPAR
R/W LRESET# 0 ^{XX0: Parity Bit is disable}
4
EPS
R/W LRESET# 0 ^{001: Parity Bit is odd.}
011: Parity Bit is even
3
PEN
R/W LRESET# 0 ^{101: Parity Bit is logic 1}
111: Parity Bit is logic 0
0: Stop bit is one bit
2
STB
R/W LRESET# 0 1: When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
00: Word length is 5 bit
01: Word length is 6 bit
1-0
WLS
R/W LRESET# 00 _{10: Word length is 7 bit}
11: Word length is 8 bit
MODEM Control Register (MCR) ⎯ Base + 4
Bit
Name
R/W Reset Default
Description
7-5
Reserved
- LRESET# - ^Reserved.
0: UART in normal condition.
4
LOOP
R/W LRESET# 0 _{1: UART is internal loop back}
3
OUT2
R/W LRESET#
0
0: All interrupt is disabled.
1: Interrupt is enabled (disabled) by IER.
2
OUT1
R/W LRESET# 0 ^{Read from MSR[6] while in loop back mode}
0: RTS# is forced to logic 1
1
RTS
R/W LRESET# 0 _{1: RTS# is forced to logic 0}
0
DTR
R/W LRESET#
0
0: DTR# is forced to logic 1
1: DTR# is forced to logic 0
Line Status Register (LSR) ⎯ Base + 5
Bit
Name
R/W Reset Default
Description
7
RCR_ERR
R LRESET#
0
0: No error in the FIFO when FIFO is enabled
1: Error in the FIFO when FIFO is enabled.
0: Transmitter is in transmitting.
6
TEMT
R LRESET# 1 _{1: Transmitter is empty.}
5
THRE
R LRESET#
1
0: Transmitter Holding Register is not empty.
1: Transmitter Holding Register is empty.
0: No break condition detected.
4
BI
R LRESET# 0 _{1: A break condition is detected.}
3
FE
R LRESET#
0
0: Data received has no frame error.
1: Data received has frame error.
0: Data received has no parity error.
2
PE
R LRESET# 0 _{1: Data received has parity error.}
1
OE
R LRESET#
0
0: No overrun condition occurred.
1: An overrun condition occurred.
0: No data is ready for read.
0
DR
R LRESET# 0 _{1: Data is received.}
112
Dec, 2011
V0.12P