F81867 Datasheet, PDF (190/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 03h The MSB of UART 1 base address.
F81867
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# F8h The LSB of UART 1 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELUR1IRQ
R/W LRESET# 4h Select the IRQ channel for UART 1.
IRQ Share Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: normal UART function
7
9BIT_MODE
R/W LRESET# 0 ^{1: enable 9-bit mode (multi-drop mode).}
In the 9-bit mode, the parity bit becomes the address/data bit.
This bit works only in 9-bit mode.
0: the SM2 bit will be cleared by host, so that data could be received.
6
AUTO_ADDR
R/W LRESET# 0 _{1: the SM2 bit will be cleared by hardware according to the sent address and}
the given address (or broadcast address derived by SADDR and SADEN)
5
RS485_INV
R/W LREST# 0 Invert RTS# if RS485_EN is set.
0: RS232 driver.
4
RS485_EN
R/W LRESET# 0 1: RS485 driver. RTS# is driven high automatically when transmitting
data, otherwise is kept low.
3-2
Reserved
-
-
- Reserved.
IRQ_MODE1 and IRQ_MODE0 will select the UART1 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
1
IRQ_MODE0
R/W LRESET# 0 ^{01 : Sharing IRQ active high edge mode.}
10 : Sharing IRQ active high Level mode.
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
0
IRQ_SHARE
R/W LRESET#
0
0 : IRQ is not sharing with the other device.
1 : IRQ is sharing with the other device.
Clock Register ⎯ Index F2h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
Select the clock source for UART1.
00: 1.8432MHz.
1-0 UART1_CLK_SEL R/W LRESET# 0 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
190
Dec, 2011
V0.12P