F81867 Datasheet, PDF (290/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7-0
CHIP_ID2
R
-
0x10 Chip ID 2.
F81867
Vendor ID 1 Register ⎯ offset 23h (Powered by I_VSB3V)
Bit
Name
R/W Reset Default
7-0
VENDOR_ID1
R
-
0x19 Vendor ID 1.
Description
Vendor ID 2 Register ⎯ offset 24h (Powered by I_VSB3V)
Bit
Name
R/W Reset Default
7-0
VENDOR_ID2
R
-
0x34 Vendor ID 2.
Description
I2C Address Register ⎯ offset 25h
Bit
Name
R/W Reset Default
Description
I2C address is used to R/W hardware monitor registers.
The default address is determined by I2C_ADDR_TRAP power on strap pin.
7-1
I2C_ADDR
R/W 5VSB 0
It could also be changed by write this byte with entry key 0x19, 0x34. The
default value is 0x2E which indicates the address is 0x5C.
0: Disable ARA.
0 EN_ARA_MODE R/W 5VSB 0
1: Enable ARA.
Clock Select Register ⎯ offset 26h
Bit
Name
R/W Reset Default
Description
The clock source of CLKIN.
00: CLKIN is 48MHz
7-6
CLK_SEL
R/W 5VSB 0 10: CLKIN is 24MHz
01: CLKIN is 14.318MHz.
10: Reserved.
5
Reserved
-
Reserved.
4 MO_PIN_LVL_SEL R/W 5VSB
MCLK/MDATA input level select.
0 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 76 input level select.
3 PIN76_LVL_SEL R/W 5VSB 0 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 71 input level select.
2 PIN71_LVL_SEL R/W 5VSB 0 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 68 input level select.
1 PIN68_LVL_SEL R/W 5VSB 1 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
PIN 67 input level select.
0 PIN67_LVL_SEL R/W 5VSB 1 0: TTL level.
1: Low level with 0.6V low and 0.9V high.
290
Dec, 2011
V0.12P