F81867 Datasheet, PDF (187/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7.11 RTC RAM Registers (LDN 0x0B)
Register
0x[HEX]
30
60
61
Register Name
RTC RAM Enable Register
Base Address High Register
Base Address Low Register
F81867
Default Value
MSB
LSB
----
-
-
-
1
0000
0
0
0
1
1001
0
1
0
1
RTC RAM Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable RTC RAM.
0
RTC_RAM_EN R/W VBAT 1
1: enable RTC RAM.
Description
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W VBAT 02h The MSB of RTC RAM base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
The LSB of RTC RAM base address.
The RTC RAM is accessed by index/data port. The index port is
7-0 BASE_ADDR_LO R/W VBAT 95h ^{{BASE_ADDR_HI, BASE_ADDR_LO[7:1],1’b0} and the data port is}
{BASE_ADDR_HI, BASE_ADDR_LO[7:1], 1’b1}. Write the index first to
select the RAM address and then read/write data port to access the context
of RAM.
7.12 H2E Configuration Registers (LDN 0x0E)
Register 0x[HEX]
Register Name
30
H2E I/O Enable Register
60
Base Address High Register
61
Base Address Low Register
70
H2E IRQ Channel Select Register
Default Value
MSB
------
000000
000000
- - - - 00
LSB
-
0
0
0
0
0
0
0
FDC Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
7-1
Reserved
-
-
- Reserved
0: disable H2E.
0
H2E_EN
R/W 5VSB 1
1: enable H2E.
Description
187
Dec, 2011
V0.12P